//////////////////////////////////////////ok
#include"stdafx.h"

#include "bochs.h"

//void BxResolveError(Ia32_Instruction_c *);

static BxExecutePtr_tR BxResolve16Mod0[8] = {
	&IA32_CPU::Resolve16Mod0Rm0,
	&IA32_CPU::Resolve16Mod0Rm1,
	&IA32_CPU::Resolve16Mod0Rm2,
	&IA32_CPU::Resolve16Mod0Rm3,
	&IA32_CPU::Resolve16Mod0Rm4,
	&IA32_CPU::Resolve16Mod0Rm5,
	&IA32_CPU::Resolve16Mod0Rm6,
	&IA32_CPU::Resolve16Mod0Rm7
};

static BxExecutePtr_tR BxResolve16Mod1or2[8] = {
	&IA32_CPU::Resolve16Mod1or2Rm0,
	&IA32_CPU::Resolve16Mod1or2Rm1,
	&IA32_CPU::Resolve16Mod1or2Rm2,
	&IA32_CPU::Resolve16Mod1or2Rm3,
	&IA32_CPU::Resolve16Mod1or2Rm4,
	&IA32_CPU::Resolve16Mod1or2Rm5,
	&IA32_CPU::Resolve16Mod1or2Rm6,
	&IA32_CPU::Resolve16Mod1or2Rm7
};

static BxExecutePtr_tR BxResolve32Mod0[8] = {
	&IA32_CPU::Resolve32Mod0Rm0,
	&IA32_CPU::Resolve32Mod0Rm1,
	&IA32_CPU::Resolve32Mod0Rm2,
	&IA32_CPU::Resolve32Mod0Rm3,
	NULL, // escape to 2-byte
	&IA32_CPU::Resolve32Mod0Rm5,
	&IA32_CPU::Resolve32Mod0Rm6,
	&IA32_CPU::Resolve32Mod0Rm7
};

static BxExecutePtr_tR BxResolve32Mod1or2[8] = {
	&IA32_CPU::Resolve32Mod1or2Rm0,
	&IA32_CPU::Resolve32Mod1or2Rm1,
	&IA32_CPU::Resolve32Mod1or2Rm2,
	&IA32_CPU::Resolve32Mod1or2Rm3,
	NULL, // escape to 2-byte
	&IA32_CPU::Resolve32Mod1or2Rm5,
	&IA32_CPU::Resolve32Mod1or2Rm6,
	&IA32_CPU::Resolve32Mod1or2Rm7
};

static BxExecutePtr_tR BxResolve32Mod0Base[8] = {
	&IA32_CPU::Resolve32Mod0Base0,
	&IA32_CPU::Resolve32Mod0Base1,
	&IA32_CPU::Resolve32Mod0Base2,
	&IA32_CPU::Resolve32Mod0Base3,
	&IA32_CPU::Resolve32Mod0Base4,
	&IA32_CPU::Resolve32Mod0Base5,
	&IA32_CPU::Resolve32Mod0Base6,
	&IA32_CPU::Resolve32Mod0Base7,
};

static BxExecutePtr_tR BxResolve32Mod1or2Base[8] = {
	&IA32_CPU::Resolve32Mod1or2Base0,
	&IA32_CPU::Resolve32Mod1or2Base1,
	&IA32_CPU::Resolve32Mod1or2Base2,
	&IA32_CPU::Resolve32Mod1or2Base3,
	&IA32_CPU::Resolve32Mod1or2Base4,
	&IA32_CPU::Resolve32Mod1or2Base5,
	&IA32_CPU::Resolve32Mod1or2Base6,
	&IA32_CPU::Resolve32Mod1or2Base7,
};

typedef struct ia32OpcodeInfo_t {
	Bit16u         Attr;
	BxExecutePtr_t ExecutePtr;
	struct ia32OpcodeInfo_t *AnotherArray;
} ia32OpcodeInfo_t;


// common fetchdecode32/64 opcode tables
#include "fetchdecode.h"


/* ************* */
/* Opcode Groups */
/* ************* */

static ia32OpcodeInfo_t BxOpcodeInfoG1EbIb[8] = {
	/* 0 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::ADD_EbIb },
	/* 1 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::OR_EbIb },
	/* 2 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::ADC_EbIb },
	/* 3 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::SBB_EbIb },
	/* 4 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::AND_EbIb },
	/* 5 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::SUB_EbIb },
	/* 6 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::XOR_EbIb },
	/* 7 */  { ia32_Immediate_Ib,              &IA32_CPU::CMP_EbIb }
};

static ia32OpcodeInfo_t BxOpcodeInfoG1Ew[8] = {
	// attributes defined in main area
	/* 0 */  { BxSplitMod11b, NULL, opcodesADD_EwIw },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::OR_EwIw },
	/* 2 */  { Ia32_Lockable, &IA32_CPU::ADC_EwIw },
	/* 3 */  { Ia32_Lockable, &IA32_CPU::SBB_EwIw },
	/* 4 */  { Ia32_Lockable, &IA32_CPU::AND_EwIw },
	/* 5 */  { Ia32_Lockable, &IA32_CPU::SUB_EwIw },
	/* 6 */  { Ia32_Lockable, &IA32_CPU::XOR_EwIw },
	/* 7 */  { 0,          &IA32_CPU::CMP_EwIw }
};

static ia32OpcodeInfo_t BxOpcodeInfoG1Ed[8] = {
	// attributes defined in main area
	/* 0 */  { BxSplitMod11b, NULL, opcodesADD_EdId },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::OR_EdId },
	/* 2 */  { Ia32_Lockable, &IA32_CPU::ADC_EdId },
	/* 3 */  { Ia32_Lockable, &IA32_CPU::SBB_EdId },
	/* 4 */  { Ia32_Lockable, &IA32_CPU::AND_EdId },
	/* 5 */  { Ia32_Lockable, &IA32_CPU::SUB_EdId },
	/* 6 */  { Ia32_Lockable, &IA32_CPU::XOR_EdId },
	/* 7 */  { 0,          &IA32_CPU::CMP_EdId }
};

static ia32OpcodeInfo_t BxOpcodeInfoG2Eb[8] = {
	// attributes defined in main area
	/* 0 */  { 0, &IA32_CPU::ROL_Eb },
	/* 1 */  { 0, &IA32_CPU::ROR_Eb },
	/* 2 */  { 0, &IA32_CPU::RCL_Eb },
	/* 3 */  { 0, &IA32_CPU::RCR_Eb },
	/* 4 */  { 0, &IA32_CPU::SHL_Eb },
	/* 5 */  { 0, &IA32_CPU::SHR_Eb },
	/* 6 */  { 0, &IA32_CPU::SHL_Eb },
	/* 7 */  { 0, &IA32_CPU::SAR_Eb }
};

static ia32OpcodeInfo_t BxOpcodeInfoG2Ew[8] = {
	// attributes defined in main area
	/* 0 */  { 0, &IA32_CPU::ROL_Ew },
	/* 1 */  { 0, &IA32_CPU::ROR_Ew },
	/* 2 */  { 0, &IA32_CPU::RCL_Ew },
	/* 3 */  { 0, &IA32_CPU::RCR_Ew },
	/* 4 */  { 0, &IA32_CPU::SHL_Ew },
	/* 5 */  { 0, &IA32_CPU::SHR_Ew },
	/* 6 */  { 0, &IA32_CPU::SHL_Ew },
	/* 7 */  { 0, &IA32_CPU::SAR_Ew }
};

static ia32OpcodeInfo_t BxOpcodeInfoG2Ed[8] = {
	// attributes defined in main area
	/* 0 */  { 0, &IA32_CPU::ROL_Ed },
	/* 1 */  { 0, &IA32_CPU::ROR_Ed },
	/* 2 */  { 0, &IA32_CPU::RCL_Ed },
	/* 3 */  { 0, &IA32_CPU::RCR_Ed },
	/* 4 */  { 0, &IA32_CPU::SHL_Ed },
	/* 5 */  { 0, &IA32_CPU::SHR_Ed },
	/* 6 */  { 0, &IA32_CPU::SHL_Ed },
	/* 7 */  { 0, &IA32_CPU::SAR_Ed }
};

static ia32OpcodeInfo_t BxOpcodeInfoG3Eb[8] = {
	/* 0 */  { ia32_Immediate_Ib, &IA32_CPU::TEST_EbIb },
	/* 1 */  { ia32_Immediate_Ib, &IA32_CPU::TEST_EbIb },
	/* 2 */  { Ia32_Lockable,     &IA32_CPU::NOT_Eb },
	/* 3 */  { Ia32_Lockable,     &IA32_CPU::NEG_Eb },
	/* 4 */  { 0,              &IA32_CPU::MUL_ALEb },
	/* 5 */  { 0,              &IA32_CPU::IMUL_ALEb },
	/* 6 */  { 0,              &IA32_CPU::DIV_ALEb },
	/* 7 */  { 0,              &IA32_CPU::IDIV_ALEb }
};

static ia32OpcodeInfo_t BxOpcodeInfoG3Ew[8] = {
	/* 0 */  { BxImmediate_Iw, &IA32_CPU::TEST_EwIw },
	/* 1 */  { BxImmediate_Iw, &IA32_CPU::TEST_EwIw },
	/* 2 */  { Ia32_Lockable,     &IA32_CPU::NOT_Ew },
	/* 3 */  { Ia32_Lockable,     &IA32_CPU::NEG_Ew },
	/* 4 */  { 0,              &IA32_CPU::MUL_AXEw },
	/* 5 */  { 0,              &IA32_CPU::IMUL_AXEw },
	/* 6 */  { 0,              &IA32_CPU::DIV_AXEw },
	/* 7 */  { 0,              &IA32_CPU::IDIV_AXEw }
};

static ia32OpcodeInfo_t BxOpcodeInfoG3Ed[8] = {
	/* 0 */  { BxImmediate_Iv, &IA32_CPU::TEST_EdId },
	/* 1 */  { BxImmediate_Iv, &IA32_CPU::TEST_EdId },
	/* 2 */  { Ia32_Lockable,     &IA32_CPU::NOT_Ed },
	/* 3 */  { Ia32_Lockable,     &IA32_CPU::NEG_Ed },
	/* 4 */  { 0,              &IA32_CPU::MUL_EAXEd },
	/* 5 */  { 0,              &IA32_CPU::IMUL_EAXEd },
	/* 6 */  { 0,              &IA32_CPU::DIV_EAXEd },
	/* 7 */  { 0,              &IA32_CPU::IDIV_EAXEd }
};

static ia32OpcodeInfo_t BxOpcodeInfoG4[8] = {
	/* 0 */  { Ia32_Lockable, &IA32_CPU::INC_Eb },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::DEC_Eb },
	/* 2 */  { 0, &IA32_CPU::BxError },
	/* 3 */  { 0, &IA32_CPU::BxError },
	/* 4 */  { 0, &IA32_CPU::BxError },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { 0, &IA32_CPU::BxError },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG5w[8] = {
	// attributes defined in main area
	/* 0 */  { Ia32_Lockable, &IA32_CPU::INC_Ew },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::DEC_Ew },
	/* 2 */  { BxMaybeJump, &IA32_CPU::CALL_Ew },
	/* 3 */  { BxMaybeJump, &IA32_CPU::CALL16_Ep },
	/* 4 */  { BxMaybeJump, &IA32_CPU::JMP_Ew },
	/* 5 */  { BxMaybeJump, &IA32_CPU::JMP16_Ep },
	/* 6 */  { 0, &IA32_CPU::PUSH_Ew },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG5d[8] = {
	// attributes defined in main area
	/* 0 */  { Ia32_Lockable, &IA32_CPU::INC_Ed },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::DEC_Ed },
	/* 2 */  { BxMaybeJump, &IA32_CPU::CALL_Ed },
	/* 3 */  { BxMaybeJump, &IA32_CPU::CALL32_Ep },
	/* 4 */  { BxMaybeJump, &IA32_CPU::JMP_Ed },
	/* 5 */  { BxMaybeJump, &IA32_CPU::JMP32_Ep },
	/* 6 */  { 0, &IA32_CPU::PUSH_Ed },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG6[8] = {
	// attributes defined in main area
	/* 0 */  { 0, &IA32_CPU::SLDT_Ew },
	/* 1 */  { 0, &IA32_CPU::STR_Ew },
	/* 2 */  { 0, &IA32_CPU::LLDT_Ew },
	/* 3 */  { 0, &IA32_CPU::LTR_Ew },
	/* 4 */  { 0, &IA32_CPU::VERR_Ew },
	/* 5 */  { 0, &IA32_CPU::VERW_Ew },
	/* 6 */  { 0, &IA32_CPU::BxError },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG7[8] = {
	/* 0 */  { 0, &IA32_CPU::SGDT_Ms },
	/* 1 */  { 0, &IA32_CPU::SIDT_Ms },
	/* 2 */  { 0, &IA32_CPU::LGDT_Ms },
	/* 3 */  { 0, &IA32_CPU::LIDT_Ms },
	/* 4 */  { 0, &IA32_CPU::SMSW_Ew },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { 0, &IA32_CPU::LMSW_Ew },
	/* 7 */  { 0, &IA32_CPU::INVLPG }
};


static ia32OpcodeInfo_t BxOpcodeInfoG8EvIb[8] = {
	/* 0 */  { 0, &IA32_CPU::BxError },
	/* 1 */  { 0, &IA32_CPU::BxError },
	/* 2 */  { 0, &IA32_CPU::BxError },
	/* 3 */  { 0, &IA32_CPU::BxError },
	/* 4 */  { ia32_Immediate_Ib,              &IA32_CPU::BT_EvIb },
	/* 5 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::BTS_EvIb },
	/* 6 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::BTR_EvIb },
	/* 7 */  { ia32_Immediate_Ib | Ia32_Lockable, &IA32_CPU::BTC_EvIb }
};

static ia32OpcodeInfo_t BxOpcodeInfoG9[8] = {
	/* 0 */  { 0, &IA32_CPU::BxError },
	/* 1 */  { Ia32_Lockable, &IA32_CPU::CMPXCHG8B },
	/* 2 */  { 0, &IA32_CPU::BxError },
	/* 3 */  { 0, &IA32_CPU::BxError },
	/* 4 */  { 0, &IA32_CPU::BxError },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { 0, &IA32_CPU::BxError },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG12[8] = {
	/* 0 */  { 0, &IA32_CPU::BxError },
	/* 1 */  { 0, &IA32_CPU::BxError },
	/* 2 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1202 },
	/* 3 */  { 0, &IA32_CPU::BxError },
	/* 4 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1204 },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1206 },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG13[8] = {
	/* 0 */  { 0, &IA32_CPU::BxError },
	/* 1 */  { 0, &IA32_CPU::BxError },
	/* 2 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1302 },
	/* 3 */  { 0, &IA32_CPU::BxError },
	/* 4 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1304 },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1306 },
	/* 7 */  { 0, &IA32_CPU::BxError }
};

static ia32OpcodeInfo_t BxOpcodeInfoG14[8] = {
	/* 0 */  { 0, &IA32_CPU::BxError },
	/* 1 */  { 0, &IA32_CPU::BxError },
	/* 2 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1402 },
	/* 3 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1403 },
	/* 4 */  { 0, &IA32_CPU::BxError },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1406 },
	/* 7 */  { ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_G1407 }
};

static ia32OpcodeInfo_t BxOpcodeInfoG15[8] = {
	/* 0 */  { 0, &IA32_CPU::FXSAVE  },
	/* 1 */  { 0, &IA32_CPU::FXRSTOR },
	/* 2 */  { 0, &IA32_CPU::LDMXCSR },
	/* 3 */  { 0, &IA32_CPU::STMXCSR },
	/* 4 */  { 0, &IA32_CPU::BxError },
	/* 5 */  { 0, &IA32_CPU::NOP },      /* LFENCE */
	/* 6 */  { 0, &IA32_CPU::NOP },      /* MFENCE */
	/* 7 */  { 0, &IA32_CPU::NOP }       /* SFENCE/CFLUSH */
};

static ia32OpcodeInfo_t BxOpcodeInfoG16[8] = {
	/* 0 */  { 0, &IA32_CPU::PREFETCH },           /* PREFETCH_NTA */
	/* 1 */  { 0, &IA32_CPU::PREFETCH },           /* PREFETCH_T0  */
	/* 2 */  { 0, &IA32_CPU::PREFETCH },           /* PREFETCH_T1  */
	/* 3 */  { 0, &IA32_CPU::PREFETCH },           /* PREFETCH_T2  */
	/* 4 */  { 0, &IA32_CPU::BxError },
	/* 5 */  { 0, &IA32_CPU::BxError },
	/* 6 */  { 0, &IA32_CPU::BxError },
	/* 7 */  { 0, &IA32_CPU::BxError }
};


/* ************************** */
/* 512 entries for 16bit mode */
/* 512 entries for 32bit mode */
/* ************************** */

static ia32OpcodeInfo_t BxOpcodeInfo[512*2] = {
	// 512 entries for 16bit mode
	/* 00 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADD_EbGb },
	/* 01 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADD_EwGw },
	/* 02 */  { BxAnother, &IA32_CPU::ADD_GbEb },
	/* 03 */  { BxAnother | BxSplitMod11b, NULL, opcodesADD_GwEw },
	/* 04 */  { ia32_Immediate_Ib, &IA32_CPU::ADD_ALIb },
	/* 05 */  { BxImmediate_Iv, &IA32_CPU::ADD_AXIw },
	/* 06 */  { 0, &IA32_CPU::PUSH_ES },
	/* 07 */  { 0, &IA32_CPU::POP_ES },
	/* 08 */  { BxAnother | Ia32_Lockable, &IA32_CPU::OR_EbGb },
	/* 09 */  { BxAnother | Ia32_Lockable, &IA32_CPU::OR_EwGw },
	/* 0A */  { BxAnother, &IA32_CPU::OR_GbEb },
	/* 0B */  { BxAnother, &IA32_CPU::OR_GwEw },
	/* 0C */  { ia32_Immediate_Ib, &IA32_CPU::OR_ALIb },
	/* 0D */  { BxImmediate_Iv, &IA32_CPU::OR_AXIw },
	/* 0E */  { 0, &IA32_CPU::PUSH_CS },
	/* 0F */  { BxAnother, &IA32_CPU::BxError }, // 2-byte escape
	/* 10 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADC_EbGb },
	/* 11 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADC_EwGw },
	/* 12 */  { BxAnother, &IA32_CPU::ADC_GbEb },
	/* 13 */  { BxAnother, &IA32_CPU::ADC_GwEw },
	/* 14 */  { ia32_Immediate_Ib, &IA32_CPU::ADC_ALIb },
	/* 15 */  { BxImmediate_Iv, &IA32_CPU::ADC_AXIw },
	/* 16 */  { 0, &IA32_CPU::PUSH_SS },
	/* 17 */  { 0, &IA32_CPU::POP_SS },
	/* 18 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SBB_EbGb },
	/* 19 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SBB_EwGw },
	/* 1A */  { BxAnother, &IA32_CPU::SBB_GbEb },
	/* 1B */  { BxAnother, &IA32_CPU::SBB_GwEw },
	/* 1C */  { ia32_Immediate_Ib, &IA32_CPU::SBB_ALIb },
	/* 1D */  { BxImmediate_Iv, &IA32_CPU::SBB_AXIw },
	/* 1E */  { 0, &IA32_CPU::PUSH_DS },
	/* 1F */  { 0, &IA32_CPU::POP_DS },
	/* 20 */  { BxAnother | Ia32_Lockable, &IA32_CPU::AND_EbGb },
	/* 21 */  { BxAnother | Ia32_Lockable, &IA32_CPU::AND_EwGw },
	/* 22 */  { BxAnother, &IA32_CPU::AND_GbEb },
	/* 23 */  { BxAnother, &IA32_CPU::AND_GwEw },
	/* 24 */  { ia32_Immediate_Ib, &IA32_CPU::AND_ALIb },
	/* 25 */  { BxImmediate_Iv, &IA32_CPU::AND_AXIw },
	/* 26 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // ES:
	/* 27 */  { 0, &IA32_CPU::DAA },
	/* 28 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SUB_EbGb },
	/* 29 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SUB_EwGw },
	/* 2A */  { BxAnother, &IA32_CPU::SUB_GbEb },
	/* 2B */  { BxAnother, &IA32_CPU::SUB_GwEw },
	/* 2C */  { ia32_Immediate_Ib, &IA32_CPU::SUB_ALIb },
	/* 2D */  { BxImmediate_Iv, &IA32_CPU::SUB_AXIw },
	/* 2E */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // CS:
	/* 2F */  { 0, &IA32_CPU::DAS },
	/* 30 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XOR_EbGb },
	/* 31 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XOR_EwGw },
	/* 32 */  { BxAnother, &IA32_CPU::XOR_GbEb },
	/* 33 */  { BxAnother, &IA32_CPU::XOR_GwEw },
	/* 34 */  { ia32_Immediate_Ib, &IA32_CPU::XOR_ALIb },
	/* 35 */  { BxImmediate_Iv, &IA32_CPU::XOR_AXIw },
	/* 36 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // SS:
	/* 37 */  { 0, &IA32_CPU::AAA },
	/* 38 */  { BxAnother, &IA32_CPU::CMP_EbGb },
	/* 39 */  { BxAnother, &IA32_CPU::CMP_EwGw },
	/* 3A */  { BxAnother, &IA32_CPU::CMP_GbEb },
	/* 3B */  { BxAnother, &IA32_CPU::CMP_GwEw },
	/* 3C */  { ia32_Immediate_Ib, &IA32_CPU::CMP_ALIb },
	/* 3D */  { BxImmediate_Iv, &IA32_CPU::CMP_AXIw },
	/* 3E */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // DS:
	/* 3F */  { 0, &IA32_CPU::AAS },
	/* 40 */  { 0, &IA32_CPU::INC_RX },
	/* 41 */  { 0, &IA32_CPU::INC_RX },
	/* 42 */  { 0, &IA32_CPU::INC_RX },
	/* 43 */  { 0, &IA32_CPU::INC_RX },
	/* 44 */  { 0, &IA32_CPU::INC_RX },
	/* 45 */  { 0, &IA32_CPU::INC_RX },
	/* 46 */  { 0, &IA32_CPU::INC_RX },
	/* 47 */  { 0, &IA32_CPU::INC_RX },
	/* 48 */  { 0, &IA32_CPU::DEC_RX },
	/* 49 */  { 0, &IA32_CPU::DEC_RX },
	/* 4A */  { 0, &IA32_CPU::DEC_RX },
	/* 4B */  { 0, &IA32_CPU::DEC_RX },
	/* 4C */  { 0, &IA32_CPU::DEC_RX },
	/* 4D */  { 0, &IA32_CPU::DEC_RX },
	/* 4E */  { 0, &IA32_CPU::DEC_RX },
	/* 4F */  { 0, &IA32_CPU::DEC_RX },
	/* 50 */  { 0, &IA32_CPU::PUSH_RX },
	/* 51 */  { 0, &IA32_CPU::PUSH_RX },
	/* 52 */  { 0, &IA32_CPU::PUSH_RX },
	/* 53 */  { 0, &IA32_CPU::PUSH_RX },
	/* 54 */  { 0, &IA32_CPU::PUSH_RX },
	/* 55 */  { 0, &IA32_CPU::PUSH_RX },
	/* 56 */  { 0, &IA32_CPU::PUSH_RX },
	/* 57 */  { 0, &IA32_CPU::PUSH_RX },
	/* 58 */  { 0, &IA32_CPU::POP_RX },
	/* 59 */  { 0, &IA32_CPU::POP_RX },
	/* 5A */  { 0, &IA32_CPU::POP_RX },
	/* 5B */  { 0, &IA32_CPU::POP_RX },
	/* 5C */  { 0, &IA32_CPU::POP_RX },
	/* 5D */  { 0, &IA32_CPU::POP_RX },
	/* 5E */  { 0, &IA32_CPU::POP_RX },
	/* 5F */  { 0, &IA32_CPU::POP_RX },
	/* 60 */  { 0, &IA32_CPU::PUSHAD16 },
	/* 61 */  { 0, &IA32_CPU::POPAD16 },
	/* 62 */  { BxAnother, &IA32_CPU::BOUND_GwMa },
	/* 63 */  { BxAnother, &IA32_CPU::ARPL_EwGw },
	/* 64 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // FS:
	/* 65 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // GS:
	/* 66 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // OS:
	/* 67 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // AS:
	/* 68 */  { BxImmediate_Iv, &IA32_CPU::PUSH_Iw },
	/* 69 */  { BxAnother | BxImmediate_Iv, &IA32_CPU::IMUL_GwEwIw },
	/* 6A */  { ia32_Immediate_Ib_SE, &IA32_CPU::PUSH_Iw },
	/* 6B */  { BxAnother | ia32_Immediate_Ib_SE, &IA32_CPU::IMUL_GwEwIw },
	/* 6C */  { BxRepeatable, &IA32_CPU::INSB_YbDX },
	/* 6D */  { BxRepeatable, &IA32_CPU::INSW_YvDX },
	/* 6E */  { BxRepeatable, &IA32_CPU::OUTSB_DXXb },
	/* 6F */  { BxRepeatable, &IA32_CPU::OUTSW_DXXv },
	/* 70 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 71 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 72 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 73 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 74 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JZ_Jw },
	/* 75 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JNZ_Jw },
	/* 76 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 77 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 78 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 79 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7A */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7B */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7C */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7D */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7E */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 7F */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jw },
	/* 80 */  { BxAnother | BxGroup1, NULL, BxOpcodeInfoG1EbIb },
	/* 81 */  { BxAnother | BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1Ew },
	/* 82 */  { BxAnother | BxGroup1, NULL, BxOpcodeInfoG1EbIb },
	/* 83 */  { BxAnother | BxGroup1 | ia32_Immediate_Ib_SE, NULL, BxOpcodeInfoG1Ew },
	/* 84 */  { BxAnother, &IA32_CPU::TEST_EbGb },
	/* 85 */  { BxAnother, &IA32_CPU::TEST_EwGw },
	/* 86 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XCHG_EbGb },
	/* 87 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XCHG_EwGw },
	/* 88 */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
	/* 89 */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EwGw },
	/* 8A */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
	/* 8B */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw },
	/* 8C */  { BxAnother, &IA32_CPU::MOV_EwSw },
	/* 8D */  { BxAnother, &IA32_CPU::LEA_GwM },
	/* 8E */  { BxAnother, &IA32_CPU::MOV_SwEw },
	/* 8F */  { BxAnother, &IA32_CPU::POP_Ew },
	/* 90 */  { 0, &IA32_CPU::NOP },
	/* 91 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 92 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 93 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 94 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 95 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 96 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 97 */  { 0, &IA32_CPU::XCHG_RXAX },
	/* 98 */  { 0, &IA32_CPU::CBW },
	/* 99 */  { 0, &IA32_CPU::CWD },
	/* 9A */  { BxMaybeJump | BxImmediate_IvIw, &IA32_CPU::CALL16_Ap },
	/* 9B */  { 0, &IA32_CPU::FWAIT },
	/* 9C */  { 0, &IA32_CPU::PUSHF_Fv },
	/* 9D */  { 0, &IA32_CPU::POPF_Fv },
	/* 9E */  { 0, &IA32_CPU::SAHF },
	/* 9F */  { 0, &IA32_CPU::LAHF },
	/* A0 */  { BxImmediate_O, &IA32_CPU::MOV_ALOb },
	/* A1 */  { BxImmediate_O, &IA32_CPU::MOV_AXOw },
	/* A2 */  { BxImmediate_O, &IA32_CPU::MOV_ObAL },
	/* A3 */  { BxImmediate_O, &IA32_CPU::MOV_OwAX },
	/* A4 */  { BxRepeatable, &IA32_CPU::MOVSB_XbYb },
	/* A5 */  { BxRepeatable, &IA32_CPU::MOVSW_XwYw },
	/* A6 */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::CMPSB_XbYb },
	/* A7 */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::CMPSW_XwYw },
	/* A8 */  { ia32_Immediate_Ib, &IA32_CPU::TEST_ALIb },
	/* A9 */  { BxImmediate_Iv, &IA32_CPU::TEST_AXIw },
	/* AA */  { BxRepeatable, &IA32_CPU::STOSB_YbAL },
	/* AB */  { BxRepeatable, &IA32_CPU::STOSW_YwAX },
	/* AC */  { BxRepeatable, &IA32_CPU::LODSB_ALXb },
	/* AD */  { BxRepeatable, &IA32_CPU::LODSW_AXXw },
	/* AE */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::SCASB_ALXb },
	/* AF */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::SCASW_AXXw },
	/* B0 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B1 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B2 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B3 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B4 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B5 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B6 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B7 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B8 */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* B9 */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BA */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BB */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BC */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BD */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BE */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* BF */  { BxImmediate_Iv, &IA32_CPU::MOV_RXIw },
	/* C0 */  { BxAnother | BxGroup2 | ia32_Immediate_Ib, NULL, BxOpcodeInfoG2Eb },
	/* C1 */  { BxAnother | BxGroup2 | ia32_Immediate_Ib, NULL, BxOpcodeInfoG2Ew },
	/* C2 */  { BxMaybeJump | BxImmediate_Iw, &IA32_CPU::RETnear16_Iw },
	/* C3 */  { BxMaybeJump,              &IA32_CPU::RETnear16 },
	/* C4 */  { BxAnother, &IA32_CPU::LES_GvMp },
	/* C5 */  { BxAnother, &IA32_CPU::LDS_GvMp },
	/* C6 */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::MOV_EbIb },
	/* C7 */  { BxAnother | BxImmediate_Iv, &IA32_CPU::MOV_EwIw },
	/* C8 */  { BxImmediate_IwIb, &IA32_CPU::ENTER_IwIb },
	/* C9 */  { 0, &IA32_CPU::LEAVE },
	/* CA */  { BxImmediate_Iw, &IA32_CPU::RETfar16_Iw },
	/* CB */  { 0, &IA32_CPU::RETfar16 },
	/* CC */  { 0, &IA32_CPU::INT3 },
	/* CD */  { ia32_Immediate_Ib, &IA32_CPU::INT_Ib },
	/* CE */  { 0, &IA32_CPU::INTO },
	/* CF */  { BxMaybeJump, &IA32_CPU::IRET16 },
	/* D0 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Eb },
	/* D1 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Ew },
	/* D2 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Eb },
	/* D3 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Ew },
	/* D4 */  { ia32_Immediate_Ib, &IA32_CPU::AAM },
	/* D5 */  { ia32_Immediate_Ib, &IA32_CPU::AAD },
	/* D6 */  { 0, &IA32_CPU::SALC },
	/* D7 */  { 0, &IA32_CPU::XLAT },
	// by default we have here pointer to the group .. as if mod <> 11b
	/* D8 */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupD8 },
	/* D9 */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupD9 },
	/* DA */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDA },
	/* DB */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDB },
	/* DC */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDC },
	/* DD */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDD },
	/* DE */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDE },
	/* DF */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDF },
	/* E0 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOPNE_Jb },
	/* E1 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOPE_Jb },
	/* E2 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOP_Jb },
	/* E3 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCXZ_Jb },
	/* E4 */  { ia32_Immediate_Ib, &IA32_CPU::IN_ALIb },
	/* E5 */  { ia32_Immediate_Ib, &IA32_CPU::IN_eAXIb },
	/* E6 */  { ia32_Immediate_Ib, &IA32_CPU::OUT_IbAL },
	/* E7 */  { ia32_Immediate_Ib, &IA32_CPU::OUT_IbeAX },
	/* E8 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::CALL_Aw },
	/* E9 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JMP_Jw },
	/* EA */  { BxMaybeJump | BxImmediate_IvIw, &IA32_CPU::JMP_Ap },
	/* EB */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JMP_Jw },
	/* EC */  { 0, &IA32_CPU::IN_ALDX },
	/* ED */  { 0, &IA32_CPU::IN_eAXDX },
	/* EE */  { 0, &IA32_CPU::OUT_DXAL },
	/* EF */  { 0, &IA32_CPU::OUT_DXeAX },
	/* F0 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // LOCK
	/* F1 */  { 0, &IA32_CPU::INT1 },
	/* F2 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // REPNE/REPNZ
	/* F3 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // REP, REPE/REPZ
	/* F4 */  { 0, &IA32_CPU::HLT },
	/* F5 */  { 0, &IA32_CPU::CMC },
	/* F6 */  { BxAnother | BxGroup3, NULL, BxOpcodeInfoG3Eb },
	/* F7 */  { BxAnother | BxGroup3, NULL, BxOpcodeInfoG3Ew },
	/* F8 */  { 0, &IA32_CPU::CLC },
	/* F9 */  { 0, &IA32_CPU::STC },
	/* FA */  { 0, &IA32_CPU::CLI },
	/* FB */  { 0, &IA32_CPU::STI },
	/* FC */  { 0, &IA32_CPU::CLD },
	/* FD */  { 0, &IA32_CPU::STD },
	/* FE */  { BxAnother | BxGroup4, NULL, BxOpcodeInfoG4 },
	/* FF */  { BxAnother | BxGroup5, NULL, BxOpcodeInfoG5w },

	/* 0F 00 */  { BxAnother | BxGroup6, NULL, BxOpcodeInfoG6 },
	/* 0F 01 */  { BxAnother | BxGroup7, NULL, BxOpcodeInfoG7 },
	/* 0F 02 */  { BxAnother, &IA32_CPU::LAR_GvEw },
	/* 0F 03 */  { BxAnother, &IA32_CPU::LSL_GvEw },
	/* 0F 04 */  { 0, &IA32_CPU::BxError },
	/* 0F 05 */  { 0, &IA32_CPU::BxError },
	/* 0F 06 */  { 0, &IA32_CPU::CLTS },
	/* 0F 07 */  { 0, &IA32_CPU::BxError },
	/* 0F 08 */  { 0, &IA32_CPU::INVD },
	/* 0F 09 */  { 0, &IA32_CPU::WBINVD },
	/* 0F 0A */  { 0, &IA32_CPU::BxError },
	/* 0F 0B */  { 0, &IA32_CPU::UndefinedOpcode }, // UD2 opcode
	/* 0F 0C */  { 0, &IA32_CPU::BxError },
	/* 0F 0D */  { 0, &IA32_CPU::BxError },
	/* 0F 0E */  { 0, &IA32_CPU::BxError },
	/* 0F 0F */  { 0, &IA32_CPU::BxError },
	/* 0F 10 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
	/* 0F 11 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
	/* 0F 12 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
	/* 0F 13 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
	/* 0F 14 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
	/* 0F 15 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
	/* 0F 16 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
	/* 0F 17 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
	/* 0F 18 */  { BxAnother | BxGroup16, NULL, BxOpcodeInfoG16 },
	/* 0F 19 */  { 0, &IA32_CPU::BxError },
	/* 0F 1A */  { 0, &IA32_CPU::BxError },
	/* 0F 1B */  { 0, &IA32_CPU::BxError },
	/* 0F 1C */  { 0, &IA32_CPU::BxError },
	/* 0F 1D */  { 0, &IA32_CPU::BxError },
	/* 0F 1E */  { 0, &IA32_CPU::BxError },
	/* 0F 1F */  { 0, &IA32_CPU::BxError },
	/* 0F 20 */  { BxAnother, &IA32_CPU::MOV_RdCd },
	/* 0F 21 */  { BxAnother, &IA32_CPU::MOV_RdDd },
	/* 0F 22 */  { BxAnother, &IA32_CPU::MOV_CdRd },
	/* 0F 23 */  { BxAnother, &IA32_CPU::MOV_DdRd },
	/* 0F 24 */  { BxAnother, &IA32_CPU::MOV_RdTd },
	/* 0F 25 */  { 0, &IA32_CPU::BxError },
	/* 0F 26 */  { BxAnother, &IA32_CPU::MOV_TdRd },
	/* 0F 27 */  { 0, &IA32_CPU::BxError },
	/* 0F 28 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
	/* 0F 29 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
	/* 0F 2A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2a },
	/* 0F 2B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2b },
	/* 0F 2C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2c },
	/* 0F 2D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2d },
	/* 0F 2E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2e },
	/* 0F 2F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2f },
	/* 0F 30 */  { 0, &IA32_CPU::WRMSR },
	/* 0F 31 */  { 0, &IA32_CPU::RDTSC },
	/* 0F 32 */  { 0, &IA32_CPU::RDMSR },
	/* 0F 33 */  { 0, &IA32_CPU::RDPMC },
	/* 0F 34 */  { 0, &IA32_CPU::SYSENTER },
	/* 0F 35 */  { 0, &IA32_CPU::SYSEXIT },
	/* 0F 36 */  { 0, &IA32_CPU::BxError },
	/* 0F 37 */  { 0, &IA32_CPU::BxError },
	/* 0F 38 */  { 0, &IA32_CPU::BxError },
	/* 0F 39 */  { 0, &IA32_CPU::BxError },
	/* 0F 3A */  { 0, &IA32_CPU::BxError },
	/* 0F 3B */  { 0, &IA32_CPU::BxError },
	/* 0F 3C */  { 0, &IA32_CPU::BxError },
	/* 0F 3D */  { 0, &IA32_CPU::BxError },
	/* 0F 3E */  { 0, &IA32_CPU::BxError },
	/* 0F 3F */  { 0, &IA32_CPU::BxError },
	/* 0F 40 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 41 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 42 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 43 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 44 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 45 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 46 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 47 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 48 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 49 */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4A */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4B */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4C */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4D */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4E */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 4F */  { BxAnother, &IA32_CPU::CMOV_GwEw },
	/* 0F 50 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f50 },
	/* 0F 51 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f51 },
	/* 0F 52 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f52 },
	/* 0F 53 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f53 },
	/* 0F 54 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f54 },
	/* 0F 55 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f55 },
	/* 0F 56 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f56 },
	/* 0F 57 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f57 },
	/* 0F 58 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f58 },
	/* 0F 59 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f59 },
	/* 0F 5A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5a },
	/* 0F 5B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5b },
	/* 0F 5C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5c },
	/* 0F 5D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5d },
	/* 0F 5E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5e },
	/* 0F 5F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5f },
	/* 0F 60 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f60 },
	/* 0F 61 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f61 },
	/* 0F 62 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f62 },
	/* 0F 63 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f63 },
	/* 0F 64 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f64 },
	/* 0F 65 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f65 },
	/* 0F 66 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f66 },
	/* 0F 67 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f67 },
	/* 0F 68 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f68 },
	/* 0F 69 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f69 },
	/* 0F 6A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6a },
	/* 0F 6B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6b },
	/* 0F 6C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6c },
	/* 0F 6D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6d },
	/* 0F 6E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6e },
	/* 0F 6F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6f },
	/* 0F 70 */  { BxAnother | ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f70 },
	/* 0F 71 */  { BxAnother | BxGroup12, NULL, BxOpcodeInfoG12 },
	/* 0F 72 */  { BxAnother | BxGroup13, NULL, BxOpcodeInfoG13 },
	/* 0F 73 */  { BxAnother | BxGroup14, NULL, BxOpcodeInfoG14 },
	/* 0F 74 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f74 },
	/* 0F 75 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f75 },
	/* 0F 76 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f76 },
	/* 0F 77 */  { 0, &IA32_CPU::EMMS },
	/* 0F 78 */  { 0, &IA32_CPU::BxError },
	/* 0F 79 */  { 0, &IA32_CPU::BxError },
	/* 0F 7A */  { 0, &IA32_CPU::BxError },
	/* 0F 7B */  { 0, &IA32_CPU::BxError },
	/* 0F 7C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7c },
	/* 0F 7D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
	/* 0F 7E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
	/* 0F 7F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
	/* 0F 80 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 81 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 82 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 83 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 84 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JZ_Jw },
	/* 0F 85 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JNZ_Jw },
	/* 0F 86 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 87 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 88 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 89 */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8A */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8B */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8C */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8D */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8E */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 8F */  { BxMaybeJump | BxImmediate_BrOff16, &IA32_CPU::JCC_Jw },
	/* 0F 90 */  { BxAnother, &IA32_CPU::SETO_Eb },
	/* 0F 91 */  { BxAnother, &IA32_CPU::SETNO_Eb },
	/* 0F 92 */  { BxAnother, &IA32_CPU::SETB_Eb },
	/* 0F 93 */  { BxAnother, &IA32_CPU::SETNB_Eb },
	/* 0F 94 */  { BxAnother, &IA32_CPU::SETZ_Eb },
	/* 0F 95 */  { BxAnother, &IA32_CPU::SETNZ_Eb },
	/* 0F 96 */  { BxAnother, &IA32_CPU::SETBE_Eb },
	/* 0F 97 */  { BxAnother, &IA32_CPU::SETNBE_Eb },
	/* 0F 98 */  { BxAnother, &IA32_CPU::SETS_Eb },
	/* 0F 99 */  { BxAnother, &IA32_CPU::SETNS_Eb },
	/* 0F 9A */  { BxAnother, &IA32_CPU::SETP_Eb },
	/* 0F 9B */  { BxAnother, &IA32_CPU::SETNP_Eb },
	/* 0F 9C */  { BxAnother, &IA32_CPU::SETL_Eb },
	/* 0F 9D */  { BxAnother, &IA32_CPU::SETNL_Eb },
	/* 0F 9E */  { BxAnother, &IA32_CPU::SETLE_Eb },
	/* 0F 9F */  { BxAnother, &IA32_CPU::SETNLE_Eb },
	/* 0F A0 */  { 0, &IA32_CPU::PUSH_FS },
	/* 0F A1 */  { 0, &IA32_CPU::POP_FS },
	/* 0F A2 */  { 0, &IA32_CPU::CPUID },
	/* 0F A3 */  { BxAnother, &IA32_CPU::BT_EwGw },
	/* 0F A4 */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::SHLD_EwGw },
	/* 0F A5 */  { BxAnother,                  &IA32_CPU::SHLD_EwGw },
	/* 0F A6 */  { 0, &IA32_CPU::CMPXCHG_XBTS },
	/* 0F A7 */  { 0, &IA32_CPU::CMPXCHG_IBTS },
	/* 0F A8 */  { 0, &IA32_CPU::PUSH_GS },
	/* 0F A9 */  { 0, &IA32_CPU::POP_GS },
	/* 0F AA */  { 0, &IA32_CPU::RSM },
	/* 0F AB */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTS_EwGw },
	/* 0F AC */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::SHRD_EwGw },
	/* 0F AD */  { BxAnother,                  &IA32_CPU::SHRD_EwGw },
	/* 0F AE */  { BxAnother | BxGroup15, NULL, BxOpcodeInfoG15 },
	/* 0F AF */  { BxAnother, &IA32_CPU::IMUL_GwEw },
	/* 0F B0 */  { BxAnother | Ia32_Lockable, &IA32_CPU::CMPXCHG_EbGb },
	/* 0F B1 */  { BxAnother | Ia32_Lockable, &IA32_CPU::CMPXCHG_EwGw },
	/* 0F B2 */  { BxAnother, &IA32_CPU::LSS_GvMp },
	/* 0F B3 */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTR_EwGw },
	/* 0F B4 */  { BxAnother, &IA32_CPU::LFS_GvMp },
	/* 0F B5 */  { BxAnother, &IA32_CPU::LGS_GvMp },
	/* 0F B6 */  { BxAnother, &IA32_CPU::MOVZX_GwEb },
	/* 0F B7 */  { BxAnother, &IA32_CPU::MOVZX_GwEw },
	/* 0F B8 */  { 0, &IA32_CPU::BxError },
	/* 0F B9 */  { 0, &IA32_CPU::UndefinedOpcode }, // UD2 opcode
	/* 0F BA */  { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
	/* 0F BB */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTC_EwGw },
	/* 0F BC */  { BxAnother, &IA32_CPU::BSF_GwEw },
	/* 0F BD */  { BxAnother, &IA32_CPU::BSR_GwEw },
	/* 0F BE */  { BxAnother, &IA32_CPU::MOVSX_GwEb },
	/* 0F BF */  { BxAnother, &IA32_CPU::MOVSX_GwEw },
	/* 0F C0 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XADD_EbGb },
	/* 0F C1 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XADD_EwGw },
	/* 0F C2 */  { BxAnother | ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
	/* 0F C3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3 },
	/* 0F C4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
	/* 0F C5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
	/* 0F C6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
	/* 0F C7 */  { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 },
	/* 0F C8 */  { 0, &IA32_CPU::BSWAP_EAX },
	/* 0F C9 */  { 0, &IA32_CPU::BSWAP_ECX },
	/* 0F CA */  { 0, &IA32_CPU::BSWAP_EDX },
	/* 0F CB */  { 0, &IA32_CPU::BSWAP_EBX },
	/* 0F CC */  { 0, &IA32_CPU::BSWAP_ESP },
	/* 0F CD */  { 0, &IA32_CPU::BSWAP_EBP },
	/* 0F CE */  { 0, &IA32_CPU::BSWAP_ESI },
	/* 0F CF */  { 0, &IA32_CPU::BSWAP_EDI },
	/* 0F D0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
	/* 0F D1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
	/* 0F D2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
	/* 0F D3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd3 },
	/* 0F D4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd4 },
	/* 0F D5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd5 },
	/* 0F D6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd6 },
	/* 0F D7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd7 },
	/* 0F D8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd8 },
	/* 0F D9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd9 },
	/* 0F DA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fda },
	/* 0F DB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdb },
	/* 0F DC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdc },
	/* 0F DD */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdd },
	/* 0F DE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fde },
	/* 0F DF */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdf },
	/* 0F E0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe0 },
	/* 0F E1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe1 },
	/* 0F E2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe2 },
	/* 0F E3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe3 },
	/* 0F E4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe4 },
	/* 0F E5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe5 },
	/* 0F E6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe6 },
	/* 0F E7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe7 },
	/* 0F E8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe8 },
	/* 0F E9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe9 },
	/* 0F EA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fea },
	/* 0F EB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0feb },
	/* 0F EC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fec },
	/* 0F ED */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fed },
	/* 0F EE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fee },
	/* 0F EF */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fef },
	/* 0F F0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff0 },
	/* 0F F1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff1 },
	/* 0F F2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff2 },
	/* 0F F3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff3 },
	/* 0F F4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff4 },
	/* 0F F5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff5 },
	/* 0F F6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff6 },
	/* 0F F7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff7 },
	/* 0F F8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff8 },
	/* 0F F9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff9 },
	/* 0F FA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffa },
	/* 0F FB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffb },
	/* 0F FC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffc },
	/* 0F FD */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffd },
	/* 0F FE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffe },
	/* 0F FF */  { 0, &IA32_CPU::BxError },

	// 512 entries for 32bit mode
	/* 00 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADD_EbGb },
	/* 01 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADD_EdGd },
	/* 02 */  { BxAnother, &IA32_CPU::ADD_GbEb },
	/* 03 */  { BxAnother | BxSplitMod11b, NULL, opcodesADD_GdEd },
	/* 04 */  { ia32_Immediate_Ib, &IA32_CPU::ADD_ALIb },
	/* 05 */  { BxImmediate_Iv, &IA32_CPU::ADD_EAXId },
	/* 06 */  { 0, &IA32_CPU::PUSH_ES },
	/* 07 */  { 0, &IA32_CPU::POP_ES },
	/* 08 */  { BxAnother | Ia32_Lockable, &IA32_CPU::OR_EbGb },
	/* 09 */  { BxAnother | Ia32_Lockable, &IA32_CPU::OR_EdGd },
	/* 0A */  { BxAnother, &IA32_CPU::OR_GbEb },
	/* 0B */  { BxAnother, &IA32_CPU::OR_GdEd },
	/* 0C */  { ia32_Immediate_Ib, &IA32_CPU::OR_ALIb },
	/* 0D */  { BxImmediate_Iv, &IA32_CPU::OR_EAXId },
	/* 0E */  { 0, &IA32_CPU::PUSH_CS },
	/* 0F */  { BxAnother, &IA32_CPU::BxError }, // 2-byte escape
	/* 10 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADC_EbGb },
	/* 11 */  { BxAnother | Ia32_Lockable, &IA32_CPU::ADC_EdGd },
	/* 12 */  { BxAnother, &IA32_CPU::ADC_GbEb },
	/* 13 */  { BxAnother, &IA32_CPU::ADC_GdEd },
	/* 14 */  { ia32_Immediate_Ib, &IA32_CPU::ADC_ALIb },
	/* 15 */  { BxImmediate_Iv, &IA32_CPU::ADC_EAXId },
	/* 16 */  { 0, &IA32_CPU::PUSH_SS },
	/* 17 */  { 0, &IA32_CPU::POP_SS },
	/* 18 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SBB_EbGb },
	/* 19 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SBB_EdGd },
	/* 1A */  { BxAnother, &IA32_CPU::SBB_GbEb },
	/* 1B */  { BxAnother, &IA32_CPU::SBB_GdEd },
	/* 1C */  { ia32_Immediate_Ib, &IA32_CPU::SBB_ALIb },
	/* 1D */  { BxImmediate_Iv, &IA32_CPU::SBB_EAXId },
	/* 1E */  { 0, &IA32_CPU::PUSH_DS },
	/* 1F */  { 0, &IA32_CPU::POP_DS },
	/* 20 */  { BxAnother | Ia32_Lockable, &IA32_CPU::AND_EbGb },
	/* 21 */  { BxAnother | Ia32_Lockable, &IA32_CPU::AND_EdGd },
	/* 22 */  { BxAnother, &IA32_CPU::AND_GbEb },
	/* 23 */  { BxAnother, &IA32_CPU::AND_GdEd },
	/* 24 */  { ia32_Immediate_Ib, &IA32_CPU::AND_ALIb },
	/* 25 */  { BxImmediate_Iv, &IA32_CPU::AND_EAXId },
	/* 26 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // ES:
	/* 27 */  { 0, &IA32_CPU::DAA },
	/* 28 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SUB_EbGb },
	/* 29 */  { BxAnother | Ia32_Lockable, &IA32_CPU::SUB_EdGd },
	/* 2A */  { BxAnother, &IA32_CPU::SUB_GbEb },
	/* 2B */  { BxAnother, &IA32_CPU::SUB_GdEd },
	/* 2C */  { ia32_Immediate_Ib, &IA32_CPU::SUB_ALIb },
	/* 2D */  { BxImmediate_Iv, &IA32_CPU::SUB_EAXId },
	/* 2E */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // CS:
	/* 2F */  { 0, &IA32_CPU::DAS },
	/* 30 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XOR_EbGb },
	/* 31 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XOR_EdGd },
	/* 32 */  { BxAnother, &IA32_CPU::XOR_GbEb },
	/* 33 */  { BxAnother, &IA32_CPU::XOR_GdEd },
	/* 34 */  { ia32_Immediate_Ib, &IA32_CPU::XOR_ALIb },
	/* 35 */  { BxImmediate_Iv, &IA32_CPU::XOR_EAXId },
	/* 36 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // SS:
	/* 37 */  { 0, &IA32_CPU::AAA },
	/* 38 */  { BxAnother, &IA32_CPU::CMP_EbGb },
	/* 39 */  { BxAnother, &IA32_CPU::CMP_EdGd },
	/* 3A */  { BxAnother, &IA32_CPU::CMP_GbEb },
	/* 3B */  { BxAnother, &IA32_CPU::CMP_GdEd },
	/* 3C */  { ia32_Immediate_Ib, &IA32_CPU::CMP_ALIb },
	/* 3D */  { BxImmediate_Iv, &IA32_CPU::CMP_EAXId },
	/* 3E */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // DS:
	/* 3F */  { 0, &IA32_CPU::AAS },
	/* 40 */  { 0, &IA32_CPU::INC_ERX },
	/* 41 */  { 0, &IA32_CPU::INC_ERX },
	/* 42 */  { 0, &IA32_CPU::INC_ERX },
	/* 43 */  { 0, &IA32_CPU::INC_ERX },
	/* 44 */  { 0, &IA32_CPU::INC_ERX },
	/* 45 */  { 0, &IA32_CPU::INC_ERX },
	/* 46 */  { 0, &IA32_CPU::INC_ERX },
	/* 47 */  { 0, &IA32_CPU::INC_ERX },
	/* 48 */  { 0, &IA32_CPU::DEC_ERX },
	/* 49 */  { 0, &IA32_CPU::DEC_ERX },
	/* 4A */  { 0, &IA32_CPU::DEC_ERX },
	/* 4B */  { 0, &IA32_CPU::DEC_ERX },
	/* 4C */  { 0, &IA32_CPU::DEC_ERX },
	/* 4D */  { 0, &IA32_CPU::DEC_ERX },
	/* 4E */  { 0, &IA32_CPU::DEC_ERX },
	/* 4F */  { 0, &IA32_CPU::DEC_ERX },
	/* 50 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 51 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 52 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 53 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 54 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 55 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 56 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 57 */  { 0, &IA32_CPU::PUSH_ERX },
	/* 58 */  { 0, &IA32_CPU::POP_ERX },
	/* 59 */  { 0, &IA32_CPU::POP_ERX },
	/* 5A */  { 0, &IA32_CPU::POP_ERX },
	/* 5B */  { 0, &IA32_CPU::POP_ERX },
	/* 5C */  { 0, &IA32_CPU::POP_ERX },
	/* 5D */  { 0, &IA32_CPU::POP_ERX },
	/* 5E */  { 0, &IA32_CPU::POP_ERX },
	/* 5F */  { 0, &IA32_CPU::POP_ERX },
	/* 60 */  { 0, &IA32_CPU::PUSHAD32 },
	/* 61 */  { 0, &IA32_CPU::POPAD32 },
	/* 62 */  { BxAnother, &IA32_CPU::BOUND_GdMa },
	/* 63 */  { BxAnother, &IA32_CPU::ARPL_EwGw },
	/* 64 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // FS:
	/* 65 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // GS:
	/* 66 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // OS:
	/* 67 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // AS:
	/* 68 */  { BxImmediate_Iv, &IA32_CPU::PUSH_Id },
	/* 69 */  { BxAnother | BxImmediate_Iv, &IA32_CPU::IMUL_GdEdId },
	/* 6A */  { ia32_Immediate_Ib_SE, &IA32_CPU::PUSH_Id },
	/* 6B */  { BxAnother | ia32_Immediate_Ib_SE, &IA32_CPU::IMUL_GdEdId },
	/* 6C */  { BxRepeatable, &IA32_CPU::INSB_YbDX },
	/* 6D */  { BxRepeatable, &IA32_CPU::INSW_YvDX },
	/* 6E */  { BxRepeatable, &IA32_CPU::OUTSB_DXXb },
	/* 6F */  { BxRepeatable, &IA32_CPU::OUTSW_DXXv },
	/* 70 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 71 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 72 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 73 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 74 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JZ_Jd },
	/* 75 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JNZ_Jd },
	/* 76 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 77 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 78 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 79 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7A */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7B */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7C */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7D */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7E */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 7F */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCC_Jd },
	/* 80 */  { BxAnother | BxGroup1, NULL, BxOpcodeInfoG1EbIb },
	/* 81 */  { BxAnother | BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1Ed },
	/* 82 */  { BxAnother | BxGroup1, NULL, BxOpcodeInfoG1EbIb },
	/* 83 */  { BxAnother | BxGroup1 | ia32_Immediate_Ib_SE, NULL, BxOpcodeInfoG1Ed },
	/* 84 */  { BxAnother, &IA32_CPU::TEST_EbGb },
	/* 85 */  { BxAnother, &IA32_CPU::TEST_EdGd },
	/* 86 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XCHG_EbGb },
	/* 87 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XCHG_EdGd },
	/* 88 */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
	/* 89 */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EdGd },
	/* 8A */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
	/* 8B */  { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GdEd },
	/* 8C */  { BxAnother, &IA32_CPU::MOV_EwSw },
	/* 8D */  { BxAnother, &IA32_CPU::LEA_GdM },
	/* 8E */  { BxAnother, &IA32_CPU::MOV_SwEw },
	/* 8F */  { BxAnother, &IA32_CPU::POP_Ed },
	/* 90 */  { 0, &IA32_CPU::NOP },
	/* 91 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 92 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 93 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 94 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 95 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 96 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 97 */  { 0, &IA32_CPU::XCHG_ERXEAX },
	/* 98 */  { 0, &IA32_CPU::CWDE },
	/* 99 */  { 0, &IA32_CPU::CDQ },
	/* 9A */  { BxMaybeJump | BxImmediate_IvIw, &IA32_CPU::CALL32_Ap },
	/* 9B */  { 0, &IA32_CPU::FWAIT },
	/* 9C */  { 0, &IA32_CPU::PUSHF_Fv },
	/* 9D */  { 0, &IA32_CPU::POPF_Fv },
	/* 9E */  { 0, &IA32_CPU::SAHF },
	/* 9F */  { 0, &IA32_CPU::LAHF },
	/* A0 */  { BxImmediate_O, &IA32_CPU::MOV_ALOb },
	/* A1 */  { BxImmediate_O, &IA32_CPU::MOV_EAXOd },
	/* A2 */  { BxImmediate_O, &IA32_CPU::MOV_ObAL },
	/* A3 */  { BxImmediate_O, &IA32_CPU::MOV_OdEAX },
	/* A4 */  { BxRepeatable, &IA32_CPU::MOVSB_XbYb },
	/* A5 */  { BxRepeatable, &IA32_CPU::MOVSD_XdYd },
	/* A6 */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::CMPSB_XbYb },
	/* A7 */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::CMPSD_XdYd },
	/* A8 */  { ia32_Immediate_Ib, &IA32_CPU::TEST_ALIb },
	/* A9 */  { BxImmediate_Iv, &IA32_CPU::TEST_EAXId },
	/* AA */  { BxRepeatable, &IA32_CPU::STOSB_YbAL },
	/* AB */  { BxRepeatable, &IA32_CPU::STOSD_YdEAX },
	/* AC */  { BxRepeatable, &IA32_CPU::LODSB_ALXb },
	/* AD */  { BxRepeatable, &IA32_CPU::LODSD_EAXXd },
	/* AE */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::SCASB_ALXb  },
	/* AF */  { BxRepeatable | BxRepeatableZF, &IA32_CPU::SCASD_EAXXd },
	/* B0 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B1 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B2 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B3 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RLIb },
	/* B4 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B5 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B6 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B7 */  { ia32_Immediate_Ib, &IA32_CPU::MOV_RHIb },
	/* B8 */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* B9 */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BA */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BB */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BC */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BD */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BE */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* BF */  { BxImmediate_Iv, &IA32_CPU::MOV_ERXId },
	/* C0 */  { BxAnother | BxGroup2 | ia32_Immediate_Ib, NULL, BxOpcodeInfoG2Eb },
	/* C1 */  { BxAnother | BxGroup2 | ia32_Immediate_Ib, NULL, BxOpcodeInfoG2Ed },
	/* C2 */  { BxMaybeJump | BxImmediate_Iw, &IA32_CPU::RETnear32_Iw },
	/* C3 */  { BxMaybeJump,              &IA32_CPU::RETnear32 },
	/* C4 */  { BxAnother, &IA32_CPU::LES_GvMp },
	/* C5 */  { BxAnother, &IA32_CPU::LDS_GvMp },
	/* C6 */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::MOV_EbIb },
	/* C7 */  { BxAnother | BxImmediate_Iv, &IA32_CPU::MOV_EdId },
	/* C8 */  { BxImmediate_IwIb, &IA32_CPU::ENTER_IwIb },
	/* C9 */  { 0, &IA32_CPU::LEAVE },
	/* CA */  { BxImmediate_Iw, &IA32_CPU::RETfar32_Iw },
	/* CB */  { 0, &IA32_CPU::RETfar32 },
	/* CC */  { 0, &IA32_CPU::INT3 },
	/* CD */  { ia32_Immediate_Ib, &IA32_CPU::INT_Ib },
	/* CE */  { 0, &IA32_CPU::INTO },
	/* CF */  { BxMaybeJump, &IA32_CPU::IRET32 },
	/* D0 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Eb },
	/* D1 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Ed },
	/* D2 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Eb },
	/* D3 */  { BxAnother | BxGroup2, NULL, BxOpcodeInfoG2Ed },
	/* D4 */  { ia32_Immediate_Ib, &IA32_CPU::AAM },
	/* D5 */  { ia32_Immediate_Ib, &IA32_CPU::AAD },
	/* D6 */  { 0, &IA32_CPU::SALC },
	/* D7 */  { 0, &IA32_CPU::XLAT },
	// by default we have here pointer to the group .. as if mod <> 11b
	/* D8 */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupD8 },
	/* D9 */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupD9 },
	/* DA */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDA },
	/* DB */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDB },
	/* DC */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDC },
	/* DD */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDD },
	/* DE */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDE },
	/* DF */  { BxAnother | BxFPGroup, NULL, BxOpcodeInfo_FPGroupDF },
	/* E0 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOPNE_Jb },
	/* E1 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOPE_Jb },
	/* E2 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::LOOP_Jb },
	/* E3 */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JCXZ_Jb },
	/* E4 */  { ia32_Immediate_Ib, &IA32_CPU::IN_ALIb },
	/* E5 */  { ia32_Immediate_Ib, &IA32_CPU::IN_eAXIb },
	/* E6 */  { ia32_Immediate_Ib, &IA32_CPU::OUT_IbAL },
	/* E7 */  { ia32_Immediate_Ib, &IA32_CPU::OUT_IbeAX },
	/* E8 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::CALL_Ad },
	/* E9 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JMP_Jd },
	/* EA */  { BxMaybeJump | BxImmediate_IvIw, &IA32_CPU::JMP_Ap },
	/* EB */  { BxMaybeJump | BxImmediate_BrOff8, &IA32_CPU::JMP_Jd },
	/* EC */  { 0, &IA32_CPU::IN_ALDX },
	/* ED */  { 0, &IA32_CPU::IN_eAXDX },
	/* EE */  { 0, &IA32_CPU::OUT_DXAL },
	/* EF */  { 0, &IA32_CPU::OUT_DXeAX },
	/* F0 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // LOCK:
	/* F1 */  { 0, &IA32_CPU::INT1 },
	/* F2 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // REPNE/REPNZ
	/* F3 */  { BxPrefix | BxAnother, &IA32_CPU::BxError }, // REP,REPE/REPZ
	/* F4 */  { 0, &IA32_CPU::HLT },
	/* F5 */  { 0, &IA32_CPU::CMC },
	/* F6 */  { BxAnother | BxGroup3, NULL, BxOpcodeInfoG3Eb },
	/* F7 */  { BxAnother | BxGroup3, NULL, BxOpcodeInfoG3Ed },
	/* F8 */  { 0, &IA32_CPU::CLC },
	/* F9 */  { 0, &IA32_CPU::STC },
	/* FA */  { 0, &IA32_CPU::CLI },
	/* FB */  { 0, &IA32_CPU::STI },
	/* FC */  { 0, &IA32_CPU::CLD },
	/* FD */  { 0, &IA32_CPU::STD },
	/* FE */  { BxAnother | BxGroup4, NULL, BxOpcodeInfoG4 },
	/* FF */  { BxAnother | BxGroup5, NULL, BxOpcodeInfoG5d },

	/* 0F 00 */  { BxAnother | BxGroup6, NULL, BxOpcodeInfoG6 },
	/* 0F 01 */  { BxAnother | BxGroup7, NULL, BxOpcodeInfoG7 },
	/* 0F 02 */  { BxAnother, &IA32_CPU::LAR_GvEw },
	/* 0F 03 */  { BxAnother, &IA32_CPU::LSL_GvEw },
	/* 0F 04 */  { 0, &IA32_CPU::BxError },
	/* 0F 05 */  { 0, &IA32_CPU::BxError },
	/* 0F 06 */  { 0, &IA32_CPU::CLTS },
	/* 0F 07 */  { 0, &IA32_CPU::BxError },
	/* 0F 08 */  { 0, &IA32_CPU::INVD },
	/* 0F 09 */  { 0, &IA32_CPU::WBINVD },
	/* 0F 0A */  { 0, &IA32_CPU::BxError },
	/* 0F 0B */  { 0, &IA32_CPU::UndefinedOpcode }, // UD2 opcode
	/* 0F 0C */  { 0, &IA32_CPU::BxError },
	/* 0F 0D */  { 0, &IA32_CPU::BxError },
	/* 0F 0E */  { 0, &IA32_CPU::BxError },
	/* 0F 0F */  { 0, &IA32_CPU::BxError },
	/* 0F 10 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
	/* 0F 11 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
	/* 0F 12 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
	/* 0F 13 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
	/* 0F 14 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
	/* 0F 15 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
	/* 0F 16 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
	/* 0F 17 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
	/* 0F 18 */  { BxAnother | BxGroup16, NULL, BxOpcodeInfoG16 },
	/* 0F 19 */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1A */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1B */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1C */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1D */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1E */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 1F */  { BxAnother, &IA32_CPU::NOP },
	/* 0F 20 */  { BxAnother, &IA32_CPU::MOV_RdCd },
	/* 0F 21 */  { BxAnother, &IA32_CPU::MOV_RdDd },
	/* 0F 22 */  { BxAnother, &IA32_CPU::MOV_CdRd },
	/* 0F 23 */  { BxAnother, &IA32_CPU::MOV_DdRd },
	/* 0F 24 */  { BxAnother, &IA32_CPU::MOV_RdTd },
	/* 0F 25 */  { 0, &IA32_CPU::BxError },
	/* 0F 26 */  { BxAnother, &IA32_CPU::MOV_TdRd },
	/* 0F 27 */  { 0, &IA32_CPU::BxError },
	/* 0F 28 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
	/* 0F 29 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
	/* 0F 2A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2a },
	/* 0F 2B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2b },
	/* 0F 2C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2c },
	/* 0F 2D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2d },
	/* 0F 2E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2e },
	/* 0F 2F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f2f },
	/* 0F 30 */  { 0, &IA32_CPU::WRMSR },
	/* 0F 31 */  { 0, &IA32_CPU::RDTSC },
	/* 0F 32 */  { 0, &IA32_CPU::RDMSR },
	/* 0F 33 */  { 0, &IA32_CPU::RDPMC },
	/* 0F 34 */  { 0, &IA32_CPU::SYSENTER },
	/* 0F 35 */  { 0, &IA32_CPU::SYSEXIT },
	/* 0F 36 */  { 0, &IA32_CPU::BxError },
	/* 0F 37 */  { 0, &IA32_CPU::BxError },
	/* 0F 38 */  { 0, &IA32_CPU::BxError },
	/* 0F 39 */  { 0, &IA32_CPU::BxError },
	/* 0F 3A */  { 0, &IA32_CPU::BxError },
	/* 0F 3B */  { 0, &IA32_CPU::BxError },
	/* 0F 3C */  { 0, &IA32_CPU::BxError },
	/* 0F 3D */  { 0, &IA32_CPU::BxError },
	/* 0F 3E */  { 0, &IA32_CPU::BxError },
	/* 0F 3F */  { 0, &IA32_CPU::BxError },
	/* 0F 40 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 41 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 42 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 43 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 44 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 45 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 46 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 47 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 48 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 49 */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4A */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4B */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4C */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4D */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4E */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 4F */  { BxAnother, &IA32_CPU::CMOV_GdEd },
	/* 0F 50 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f50 },
	/* 0F 51 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f51 },
	/* 0F 52 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f52 },
	/* 0F 53 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f53 },
	/* 0F 54 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f54 },
	/* 0F 55 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f55 },
	/* 0F 56 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f56 },
	/* 0F 57 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f57 },
	/* 0F 58 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f58 },
	/* 0F 59 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f59 },
	/* 0F 5A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5a },
	/* 0F 5B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5b },
	/* 0F 5C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5c },
	/* 0F 5D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5d },
	/* 0F 5E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5e },
	/* 0F 5F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f5f },
	/* 0F 60 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f60 },
	/* 0F 61 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f61 },
	/* 0F 62 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f62 },
	/* 0F 63 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f63 },
	/* 0F 64 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f64 },
	/* 0F 65 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f65 },
	/* 0F 66 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f66 },
	/* 0F 67 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f67 },
	/* 0F 68 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f68 },
	/* 0F 69 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f69 },
	/* 0F 6A */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6a },
	/* 0F 6B */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6b },
	/* 0F 6C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6c },
	/* 0F 6D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6d },
	/* 0F 6E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6e },
	/* 0F 6F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6f },
	/* 0F 70 */  { BxAnother | ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f70 },
	/* 0F 71 */  { BxAnother | BxGroup12, NULL, BxOpcodeInfoG12 },
	/* 0F 72 */  { BxAnother | BxGroup13, NULL, BxOpcodeInfoG13 },
	/* 0F 73 */  { BxAnother | BxGroup14, NULL, BxOpcodeInfoG14 },
	/* 0F 74 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f74 },
	/* 0F 75 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f75 },
	/* 0F 76 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f76 },
	/* 0F 77 */  { 0, &IA32_CPU::EMMS },
	/* 0F 78 */  { 0, &IA32_CPU::BxError },
	/* 0F 79 */  { 0, &IA32_CPU::BxError },
	/* 0F 7A */  { 0, &IA32_CPU::BxError },
	/* 0F 7B */  { 0, &IA32_CPU::BxError },
	/* 0F 7C */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7c },
	/* 0F 7D */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
	/* 0F 7E */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
	/* 0F 7F */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
	/* 0F 80 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 81 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 82 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 83 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 84 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JZ_Jd },
	/* 0F 85 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JNZ_Jd },
	/* 0F 86 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 87 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 88 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 89 */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8A */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8B */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8C */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8D */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8E */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 8F */  { BxMaybeJump | BxImmediate_BrOff32, &IA32_CPU::JCC_Jd },
	/* 0F 90 */  { BxAnother, &IA32_CPU::SETO_Eb },
	/* 0F 91 */  { BxAnother, &IA32_CPU::SETNO_Eb },
	/* 0F 92 */  { BxAnother, &IA32_CPU::SETB_Eb },
	/* 0F 93 */  { BxAnother, &IA32_CPU::SETNB_Eb },
	/* 0F 94 */  { BxAnother, &IA32_CPU::SETZ_Eb },
	/* 0F 95 */  { BxAnother, &IA32_CPU::SETNZ_Eb },
	/* 0F 96 */  { BxAnother, &IA32_CPU::SETBE_Eb },
	/* 0F 97 */  { BxAnother, &IA32_CPU::SETNBE_Eb },
	/* 0F 98 */  { BxAnother, &IA32_CPU::SETS_Eb },
	/* 0F 99 */  { BxAnother, &IA32_CPU::SETNS_Eb },
	/* 0F 9A */  { BxAnother, &IA32_CPU::SETP_Eb },
	/* 0F 9B */  { BxAnother, &IA32_CPU::SETNP_Eb },
	/* 0F 9C */  { BxAnother, &IA32_CPU::SETL_Eb },
	/* 0F 9D */  { BxAnother, &IA32_CPU::SETNL_Eb },
	/* 0F 9E */  { BxAnother, &IA32_CPU::SETLE_Eb },
	/* 0F 9F */  { BxAnother, &IA32_CPU::SETNLE_Eb },
	/* 0F A0 */  { 0, &IA32_CPU::PUSH_FS },
	/* 0F A1 */  { 0, &IA32_CPU::POP_FS },
	/* 0F A2 */  { 0, &IA32_CPU::CPUID },
	/* 0F A3 */  { BxAnother, &IA32_CPU::BT_EdGd },
	/* 0F A4 */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::SHLD_EdGd },
	/* 0F A5 */  { BxAnother,                  &IA32_CPU::SHLD_EdGd },
	/* 0F A6 */  { 0, &IA32_CPU::CMPXCHG_XBTS },
	/* 0F A7 */  { 0, &IA32_CPU::CMPXCHG_IBTS },
	/* 0F A8 */  { 0, &IA32_CPU::PUSH_GS },
	/* 0F A9 */  { 0, &IA32_CPU::POP_GS },
	/* 0F AA */  { 0, &IA32_CPU::RSM },
	/* 0F AB */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTS_EdGd },
	/* 0F AC */  { BxAnother | ia32_Immediate_Ib, &IA32_CPU::SHRD_EdGd },
	/* 0F AD */  { BxAnother,                  &IA32_CPU::SHRD_EdGd },
	/* 0F AE */  { BxAnother | BxGroup15, NULL, BxOpcodeInfoG15 },
	/* 0F AF */  { BxAnother, &IA32_CPU::IMUL_GdEd },
	/* 0F B0 */  { BxAnother | Ia32_Lockable, &IA32_CPU::CMPXCHG_EbGb },
	/* 0F B1 */  { BxAnother | Ia32_Lockable, &IA32_CPU::CMPXCHG_EdGd },
	/* 0F B2 */  { BxAnother, &IA32_CPU::LSS_GvMp },
	/* 0F B3 */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTR_EdGd },
	/* 0F B4 */  { BxAnother, &IA32_CPU::LFS_GvMp },
	/* 0F B5 */  { BxAnother, &IA32_CPU::LGS_GvMp },
	/* 0F B6 */  { BxAnother, &IA32_CPU::MOVZX_GdEb },
	/* 0F B7 */  { BxAnother, &IA32_CPU::MOVZX_GdEw },
	/* 0F B8 */  { 0, &IA32_CPU::BxError },
	/* 0F B9 */  { 0, &IA32_CPU::UndefinedOpcode }, // UD2 opcode
	/* 0F BA */  { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
	/* 0F BB */  { BxAnother | Ia32_Lockable, &IA32_CPU::BTC_EdGd },
	/* 0F BC */  { BxAnother, &IA32_CPU::BSF_GdEd },
	/* 0F BD */  { BxAnother, &IA32_CPU::BSR_GdEd },
	/* 0F BE */  { BxAnother, &IA32_CPU::MOVSX_GdEb },
	/* 0F BF */  { BxAnother, &IA32_CPU::MOVSX_GdEw },
	/* 0F C0 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XADD_EbGb },
	/* 0F C1 */  { BxAnother | Ia32_Lockable, &IA32_CPU::XADD_EdGd },
	/* 0F C2 */  { BxAnother | ia32_Immediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
	/* 0F C3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3 },
	/* 0F C4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
	/* 0F C5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
	/* 0F C6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
	/* 0F C7 */  { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 },
	/* 0F C8 */  { 0, &IA32_CPU::BSWAP_EAX },
	/* 0F C9 */  { 0, &IA32_CPU::BSWAP_ECX },
	/* 0F CA */  { 0, &IA32_CPU::BSWAP_EDX },
	/* 0F CB */  { 0, &IA32_CPU::BSWAP_EBX },
	/* 0F CC */  { 0, &IA32_CPU::BSWAP_ESP },
	/* 0F CD */  { 0, &IA32_CPU::BSWAP_EBP },
	/* 0F CE */  { 0, &IA32_CPU::BSWAP_ESI },
	/* 0F CF */  { 0, &IA32_CPU::BSWAP_EDI },
	/* 0F D0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
	/* 0F D1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
	/* 0F D2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
	/* 0F D3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd3 },
	/* 0F D4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd4 },
	/* 0F D5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd5 },
	/* 0F D6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd6 },
	/* 0F D7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd7 },
	/* 0F D8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd8 },
	/* 0F D9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd9 },
	/* 0F DA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fda },
	/* 0F DB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdb },
	/* 0F DC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdc },
	/* 0F DD */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdd },
	/* 0F DE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fde },
	/* 0F DF */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fdf },
	/* 0F E0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe0 },
	/* 0F E1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe1 },
	/* 0F E2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe2 },
	/* 0F E3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe3 },
	/* 0F E4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe4 },
	/* 0F E5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe5 },
	/* 0F E6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe6 },
	/* 0F E7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe7 },
	/* 0F E8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe8 },
	/* 0F E9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fe9 },
	/* 0F EA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fea },
	/* 0F EB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0feb },
	/* 0F EC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fec },
	/* 0F ED */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fed },
	/* 0F EE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fee },
	/* 0F EF */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fef },
	/* 0F F0 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff0 },
	/* 0F F1 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff1 },
	/* 0F F2 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff2 },
	/* 0F F3 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff3 },
	/* 0F F4 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff4 },
	/* 0F F5 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff5 },
	/* 0F F6 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff6 },
	/* 0F F7 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff7 },
	/* 0F F8 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff8 },
	/* 0F F9 */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ff9 },
	/* 0F FA */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffa },
	/* 0F FB */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffb },
	/* 0F FC */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffc },
	/* 0F FD */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffd },
	/* 0F FE */  { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0ffe },
	/* 0F FF */  { 0, &IA32_CPU::BxError }
};

//unsigned  IA32_CPU::fetchDecodeNoException(Bit8u *iptr, Ia32_Instruction_c *instruction,unsigned remain)
//{
//
//	bx_bool is_32, lock=0;
//	unsigned b1, b2, ilen=1, attr, os_32;
//	unsigned imm_mode, offset;
//	unsigned rm, mod=0, nnn=0;
//	unsigned sse_prefix;
//
//#define IA32_SSE_PREFIX_NONE 0
//#define IA32_SSE_PREFIX_66   1
//#define IA32_SSE_PREFIX_F2   2
//#define IA32_SSE_PREFIX_F3   4      /* only one SSE prefix could be used */
//	static int sse_prefix_index[8] = { 0, 1, 2, -1, 3, -1, -1, -1 };
//	os_32 = is_32 =sregs[IA32_SEG_REG_CS].cache.u.segment.d_b;
//	instruction->ResolveModrm = NULL;
//	instruction->initMetaInfo(IA32_SEG_REG_NULL,/*os32*/   is_32,  /*as32*/ is_32, /*os64*/  0,  /*as64*/  0);
//	sse_prefix = IA32_SSE_PREFIX_NONE;
//
//fetch_b1:
//	b1 = *iptr++;
//
//another_byte:
//	offset = os_32 << 9; // * 512
//	attr = BxOpcodeInfo[b1+offset].Attr;
//	instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
//
//	if (attr & BxAnother)
//	{
//		if (attr & BxPrefix)
//		{
//
//			switch (b1)
//			{
//			case 0x66: // OpSize
//				os_32 = !is_32;
//				sse_prefix |= IA32_SSE_PREFIX_66;
//				instruction->setOs32B(os_32);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//
//			case 0x67: // AddrSize
//				instruction->setAs32B(!is_32);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//
//			case 0xf2: // REPNE/REPNZ
//				sse_prefix |= IA32_SSE_PREFIX_F2;
//				instruction->setRepUsed(b1 & 3);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//
//			case 0xf3: // REP/REPE/REPZ
//				sse_prefix |= IA32_SSE_PREFIX_F3;
//				instruction->setRepUsed(b1 & 3);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//
//			case 0x2e: // CS:
//				instruction->setSeg(IA32_SEG_REG_CS);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0x26: // ES:
//				instruction->setSeg(IA32_SEG_REG_ES);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0x36: // SS:
//				instruction->setSeg(IA32_SEG_REG_SS);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0x3e: // DS:
//				instruction->setSeg(IA32_SEG_REG_DS);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0x64: // FS:
//				instruction->setSeg(IA32_SEG_REG_FS);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0x65: // GS:
//				instruction->setSeg(IA32_SEG_REG_GS);
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			case 0xf0: // LOCK:
//				lock = 1;
//				if (ilen < remain)
//				{
//					ilen++;
//					goto fetch_b1;
//				}
//				return(0);
//			default:
//				return(0);
//			}
//		}
//
//		// opcode requires another byte
//		if (ilen < remain)
//		{
//			ilen++;
//			b2 = *iptr++;
//			if (b1 == 0x0f)
//			{
//				// 2-byte prefix
//				b1 = 0x100 | b2;
//				goto another_byte;
//			}
//		}
//		else
//			return(0);
//
//		// Parse mod-nnn-rm and related bytes
//		mod   = b2 & 0xc0; // leave unshifted
//		nnn   = (b2 >> 3) & 0x07;
//		rm    = b2 & 0x07;
//		instruction->modRMForm.modRMData = (b2<<20);
//		instruction->modRMForm.modRMData |= mod;
//		instruction->modRMForm.modRMData |= (nnn<<8);
//		instruction->modRMForm.modRMData |= rm;
//
//		// MOVs with CRx and DRx always use register ops and ignore the mod field.
//		if ( (b1 & ~3) == 0x120 )
//			mod = 0xc0;
//
//		if (mod == 0xc0)
//		{ // mod == 11b
//			instruction->metaInfo |= (1<<22); // (modC0)
//			goto modrm_done;
//		}
//
//		if (instruction->as32L())
//		{
//			// 32-bit addressing modes; note that mod==11b handled above
//			if (rm != 4)
//			{ // no s-i-b byte
//				if (mod == 0x00)
//				{ // mod == 00b
//					instruction->ResolveModrm = BxResolve32Mod0[rm];
//					if (IA32_NULL_SEG_REG(instruction->seg()))
//						instruction->setSeg(IA32_SEG_REG_DS);
//					if (rm == 5)
//					{
//						if ((ilen+3) < remain)
//						{
//							instruction->modRMForm.displ32u = FetchDWORD(iptr);
//							iptr += 4;
//							ilen += 4;
//							goto modrm_done;
//						}
//						else
//							return(0);
//					}
//					// mod==00b, rm!=4, rm!=5
//					goto modrm_done;
//				}
//				if (mod == 0x40)
//				{ // mod == 01b
//					instruction->ResolveModrm = BxResolve32Mod1or2[rm];
//					if (IA32_NULL_SEG_REG(instruction->seg()))
//						instruction->setSeg( sreg_mod01or10_rm32[rm]);
//get_8bit_displ:
//					if (ilen < remain)
//					{
//						// 8 sign extended to 32
//						instruction->modRMForm.displ32u = (Bit8s) *iptr++;
//						ilen++;
//						goto modrm_done;
//					}
//					else return(0);
//				}
//				// (mod == 0x80) mod == 10b
//				instruction->ResolveModrm = BxResolve32Mod1or2[rm];
//				if (IA32_NULL_SEG_REG(instruction->seg()))
//					instruction->setSeg( sreg_mod01or10_rm32[rm]);
//get_32bit_displ:
//				if ((ilen+3) < remain)
//				{
//					instruction->modRMForm.displ32u = FetchDWORD(iptr);
//					iptr += 4;
//					ilen += 4;
//					goto modrm_done;
//				}
//				else return(0);
//			}
//			else
//			{ // mod!=11b, rm==4, s-i-b byte follows
//				unsigned sib, base, index, scale;
//				if (ilen < remain)
//				{
//					sib = *iptr++;
//					ilen++;
//				}
//				else
//				{
//					return(0);
//				}
//				base  = sib & 0x07; sib >>= 3;
//				index = sib & 0x07; sib >>= 3;
//				scale = sib;
//				instruction->modRMForm.modRMData |= (base<<12);
//				instruction->modRMForm.modRMData |= (index<<16);
//				instruction->modRMForm.modRMData |= (scale<<4);
//				if (mod == 0x00)
//				{ // mod==00b, rm==4
//					instruction->ResolveModrm = BxResolve32Mod0Base[base];
//					if (IA32_NULL_SEG_REG(instruction->seg()))
//						instruction->setSeg( sreg_mod0_base32[base]);
//					if (base == 0x05)
//						goto get_32bit_displ;
//					// mod==00b, rm==4, base!=5
//					goto modrm_done;
//				}
//				if (mod == 0x40)
//				{ // mod==01b, rm==4
//					instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
//					if (IA32_NULL_SEG_REG(instruction->seg()))
//						instruction->setSeg( sreg_mod1or2_base32[base]);
//					goto get_8bit_displ;
//				}
//				// (mod == 0x80),  mod==10b, rm==4
//				instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
//				if (IA32_NULL_SEG_REG(instruction->seg()))
//					instruction->setSeg( sreg_mod1or2_base32[base]);
//				goto get_32bit_displ;
//			}
//		}
//		else
//		{
//			// 16-bit addressing modes, mod==11b handled above
//			if (mod == 0x40)
//			{ // mod == 01b
//				instruction->ResolveModrm = BxResolve16Mod1or2[rm];
//				if (IA32_NULL_SEG_REG(instruction->seg()))
//					instruction->setSeg( sreg_mod01or10_rm16[rm]);
//				if (ilen < remain)
//				{
//					// 8 sign extended to 16
//					instruction->modRMForm.displ16u = (Bit8s) *iptr++;
//					ilen++;
//					goto modrm_done;
//				}
//				else
//					return(0);
//			}
//			if (mod == 0x80)
//			{ // mod == 10b
//				instruction->ResolveModrm = BxResolve16Mod1or2[rm];
//				if (IA32_NULL_SEG_REG(instruction->seg()))
//					instruction->setSeg( sreg_mod01or10_rm16[rm]);
//				if ((ilen+1) < remain)
//				{
//					instruction->modRMForm.displ16u = FetchWORD(iptr);
//					iptr += 2;
//					ilen += 2;
//					goto modrm_done;
//				}
//				else return(0);
//			}
//			// mod must be 00b at this point
//			instruction->ResolveModrm = BxResolve16Mod0[rm];
//			if (IA32_NULL_SEG_REG(instruction->seg()))
//				instruction->setSeg( sreg_mod00_rm16[rm]);
//			if (rm == 0x06)
//			{
//				if ((ilen+1) < remain)
//				{
//					instruction->modRMForm.displ16u = FetchWORD(iptr);
//					iptr += 2;
//					ilen += 2;
//					goto modrm_done;
//				}
//				else
//					return(0);
//			}
//			// mod=00b rm!=6
//		}
//
//modrm_done:
//
//		// Resolve ExecutePtr and additional opcode Attr
//		ia32OpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo[b1+offset]);
//		while(attr & BxGroupX)
//		{
//			Bit32u Group = attr & BxGroupX;
//			attr &= ~BxGroupX;
//
//			switch(Group) {
//			case BxGroupN:
//				OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
//				break;
//			case BxPrefixSSE:
//				{
//					/* For SSE opcodes, look into another 4 entries table
//					with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
//					int op = sse_prefix_index[sse_prefix];
//					if (op < 0)
//					{
//						//BX_INFO(("fetchdecode: SSE opcode with two or more prefixes"));
//						return(0);
//					}
//					OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[op]);
//					break;
//				}
//			case BxSplitMod11b:
//				/* For high frequency opcodes, two variants of the instruction are
//				* implemented; one for the mod=11b case (Reg-Reg), and one for
//				* the other cases (Reg-Mem).  If this is one of those cases,
//				* we need to dereference to get to the execute pointer.
//				*/
//				OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[mod==0xc0]);
//				break;
//			case BxFPGroup:
//				if (mod != 0xc0)  // mod != 11b
//					OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
//				else
//				{
//					int index = (b1-0xD8)*64 + (0x3f & b2);
//					OpcodeInfoPtr = &(BxOpcodeInfo_FloatingPoint[index]);
//				}
//				break;
//			default:
//				break;
//			}
//
//			/* get additional attributes from group table */
//			attr |= OpcodeInfoPtr->Attr;
//		}
//
//		instruction->execute = OpcodeInfoPtr->ExecutePtr;
//		instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
//	}
//	else
//	{
//		instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
//		instruction->IxForm.opcodeReg = b1 & 7;
//	}
//
//	if (lock)
//	{
//		if ((mod == 0xc0) || !(attr & Ia32_Lockable))
//		{
//			return(0);
//		}
//	}
//
//	imm_mode = attr & BxImmediate;
//	if (imm_mode)
//	{
//		switch (imm_mode)
//		{
//		case ia32_Immediate_Ib:
//			if (ilen < remain)
//			{
//				instruction->modRMForm.Ib = *iptr;
//				ilen++;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		case ia32_Immediate_Ib_SE: // Sign extend to OS size
//			if (ilen < remain)
//			{
//				Bit8s temp8s = *iptr;
//				if (instruction->os32L())
//					instruction->modRMForm.Id = (Bit32s) temp8s;
//				else
//					instruction->modRMForm.Iw = (Bit16s) temp8s;
//				ilen++;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		case BxImmediate_Iv: // same as BxImmediate_BrOff32
//		case BxImmediate_IvIw: // CALL_Ap
//			if (instruction->os32L())
//			{
//				if ((ilen+3) < remain)
//				{
//					instruction->modRMForm.Id = FetchDWORD(iptr);
//					iptr += 4;
//					ilen += 4;
//				}
//				else
//					return(0);
//			}
//			else
//			{
//				if ((ilen+1) < remain)
//				{
//					instruction->modRMForm.Iw = FetchWORD(iptr);
//					iptr += 2;
//					ilen += 2;
//				}
//				else return(0);
//			}
//			if (imm_mode != BxImmediate_IvIw)
//				break;
//			// Get Iw for BxImmediate_IvIw
//			if ((ilen+1) < remain)
//			{
//				instruction->IxIxForm.Iw2 = FetchWORD(iptr);
//				ilen += 2;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		case BxImmediate_O:
//			// For instructions which embed the address in the opcode.
//			if (instruction->as32L())
//			{
//				// fetch 32bit address into Id
//				if ((ilen+3) < remain)
//				{
//					instruction->modRMForm.Id = FetchDWORD(iptr);
//					ilen += 4;
//				}
//				else return(0);
//			}
//			else
//			{
//				// fetch 16bit address into Id
//				if ((ilen+1) < remain)
//				{
//					instruction->modRMForm.Id = (Bit32u) FetchWORD(iptr);
//					ilen += 2;
//				}
//				else return(0);
//			}
//			if (IA32_NULL_SEG_REG(instruction->seg()))
//				instruction->setSeg(IA32_SEG_REG_DS);
//			break;
//		case BxImmediate_Iw:
//		case BxImmediate_IwIb:
//			if ((ilen+1) < remain)
//			{
//				instruction->modRMForm.Iw = FetchWORD(iptr);
//				iptr += 2;
//				ilen += 2;
//			}
//			else
//			{
//				return(0);
//			}
//			if (imm_mode == BxImmediate_Iw) break;
//			if (ilen < remain)
//			{
//				instruction->IxIxForm.Ib2 = *iptr;
//				ilen++;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		case BxImmediate_BrOff8:
//			if (ilen < remain)
//			{
//				Bit8s temp8s = *iptr;
//				instruction->modRMForm.Id = temp8s;
//				ilen++;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		case BxImmediate_BrOff16:
//			if ((ilen+1) < remain)
//			{
//				instruction->modRMForm.Id = (Bit16s) FetchWORD(iptr);
//				ilen += 2;
//			}
//			else
//			{
//				return(0);
//			}
//			break;
//		default:
//			break;
//		}
//	}
//
//	instruction->setB1(b1);
//	instruction->setILen(ilen);
//	return(1);
//}

unsigned  IA32_CPU::fetchDecode( Bit8u *iptr, Ia32_Instruction_c *instruction, unsigned remain)
{

	bx_bool is_32, lock=0;
	unsigned b1, b2, ilen=1, attr, os_32;
	unsigned imm_mode, offset;
	unsigned rm, mod=0, nnn=0;
	unsigned sse_prefix;

#define IA32_SSE_PREFIX_NONE 0
#define IA32_SSE_PREFIX_66   1
#define IA32_SSE_PREFIX_F2   2
#define IA32_SSE_PREFIX_F3   4      /* only one SSE prefix could be used */

	static int sse_prefix_index[8] = { 0, 1, 2, -1, 3, -1, -1, -1 };
	os_32 = is_32 =sregs[IA32_SEG_REG_CS].cache.u.segment.d_b;
	instruction->ResolveModrm = NULL;
	instruction->initMetaInfo(IA32_SEG_REG_NULL,/*os32*/   is_32,  /*as32*/ is_32, /*os64*/  0,  /*as64*/  0);
	sse_prefix = IA32_SSE_PREFIX_NONE;

fetch_b1:
	b1 = *iptr++;

another_byte:
	offset = os_32 << 9; // * 512
	attr = BxOpcodeInfo[b1+offset].Attr;
	instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));

	if (attr & BxAnother)
	{
		if (attr & BxPrefix)
		{

			switch (b1)
			{
			case 0x66: // OpSize
				os_32 = !is_32;
				sse_prefix |= IA32_SSE_PREFIX_66;
				instruction->setOs32B(os_32);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);

			case 0x67: // AddrSize
				instruction->setAs32B(!is_32);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);

			case 0xf2: // REPNE/REPNZ
				sse_prefix |= IA32_SSE_PREFIX_F2;
				instruction->setRepUsed(b1 & 3);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);

			case 0xf3: // REP/REPE/REPZ
				sse_prefix |= IA32_SSE_PREFIX_F3;
				instruction->setRepUsed(b1 & 3);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);

			case 0x2e: // CS:
				instruction->setSeg(IA32_SEG_REG_CS);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0x26: // ES:
				instruction->setSeg(IA32_SEG_REG_ES);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0x36: // SS:
				instruction->setSeg(IA32_SEG_REG_SS);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0x3e: // DS:
				instruction->setSeg(IA32_SEG_REG_DS);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0x64: // FS:
				instruction->setSeg(IA32_SEG_REG_FS);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0x65: // GS:
				instruction->setSeg(IA32_SEG_REG_GS);
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			case 0xf0: // LOCK:
				lock = 1;
				if (ilen < remain)
				{
					ilen++;
					goto fetch_b1;
				}
				return(0);
			default:
				return(0);
			}
		}

		// opcode requires another byte
		if (ilen < remain)
		{
			ilen++;
			b2 = *iptr++;
			if (b1 == 0x0f)
			{
				// 2-byte prefix
				b1 = 0x100 | b2;
				goto another_byte;
			}
		}
		else
			return(0);

		// Parse mod-nnn-rm and related bytes
		mod   = b2 & 0xc0; // leave unshifted
		nnn   = (b2 >> 3) & 0x07;
		rm    = b2 & 0x07;
		instruction->modRMForm.modRMData = (b2<<20);
		instruction->modRMForm.modRMData |= mod;
		instruction->modRMForm.modRMData |= (nnn<<8);
		instruction->modRMForm.modRMData |= rm;

		// MOVs with CRx and DRx always use register ops and ignore the mod field.
		if ( (b1 & ~3) == 0x120 )
			mod = 0xc0;

		if (mod == 0xc0)
		{ // mod == 11b
			instruction->metaInfo |= (1<<22); // (modC0)
			goto modrm_done;
		}

		if (instruction->as32L())
		{
			// 32-bit addressing modes; note that mod==11b handled above
			if (rm != 4)
			{ // no s-i-b byte
				if (mod == 0x00)
				{ // mod == 00b
					instruction->ResolveModrm = BxResolve32Mod0[rm];
					if (IA32_NULL_SEG_REG(instruction->seg()))
						instruction->setSeg(IA32_SEG_REG_DS);
					if (rm == 5)
					{
						if ((ilen+3) < remain)
						{
							instruction->modRMForm.displ32u = FetchDWORD(iptr);
							iptr += 4;
							ilen += 4;
							goto modrm_done;
						}
						else
							return(0);
					}
					// mod==00b, rm!=4, rm!=5
					goto modrm_done;
				}
				if (mod == 0x40)
				{ // mod == 01b
					instruction->ResolveModrm = BxResolve32Mod1or2[rm];
					if (IA32_NULL_SEG_REG(instruction->seg()))
						instruction->setSeg( sreg_mod01or10_rm32[rm]);
get_8bit_displ:
					if (ilen < remain)
					{
						// 8 sign extended to 32
						instruction->modRMForm.displ32u = (Bit8s) *iptr++;
						ilen++;
						goto modrm_done;
					}
					else return(0);
				}
				// (mod == 0x80) mod == 10b
				instruction->ResolveModrm = BxResolve32Mod1or2[rm];
				if (IA32_NULL_SEG_REG(instruction->seg()))
					instruction->setSeg( sreg_mod01or10_rm32[rm]);
get_32bit_displ:
				if ((ilen+3) < remain)
				{
					instruction->modRMForm.displ32u = FetchDWORD(iptr);
					iptr += 4;
					ilen += 4;
					goto modrm_done;
				}
				else return(0);
			}
			else
			{ // mod!=11b, rm==4, s-i-b byte follows
				unsigned sib, base, index, scale;
				if (ilen < remain)
				{
					sib = *iptr++;
					ilen++;
				}
				else
				{
					return(0);
				}
				base  = sib & 0x07; sib >>= 3;
				index = sib & 0x07; sib >>= 3;
				scale = sib;
				instruction->modRMForm.modRMData |= (base<<12);
				instruction->modRMForm.modRMData |= (index<<16);
				instruction->modRMForm.modRMData |= (scale<<4);
				if (mod == 0x00)
				{ // mod==00b, rm==4
					instruction->ResolveModrm = BxResolve32Mod0Base[base];
					if (IA32_NULL_SEG_REG(instruction->seg()))
						instruction->setSeg( sreg_mod0_base32[base]);
					if (base == 0x05)
						goto get_32bit_displ;
					// mod==00b, rm==4, base!=5
					goto modrm_done;
				}
				if (mod == 0x40)
				{ // mod==01b, rm==4
					instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
					if (IA32_NULL_SEG_REG(instruction->seg()))
						instruction->setSeg( sreg_mod1or2_base32[base]);
					goto get_8bit_displ;
				}
				// (mod == 0x80),  mod==10b, rm==4
				instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
				if (IA32_NULL_SEG_REG(instruction->seg()))
					instruction->setSeg( sreg_mod1or2_base32[base]);
				goto get_32bit_displ;
			}
		}
		else
		{
			// 16-bit addressing modes, mod==11b handled above
			if (mod == 0x40)
			{ // mod == 01b
				instruction->ResolveModrm = BxResolve16Mod1or2[rm];
				if (IA32_NULL_SEG_REG(instruction->seg()))
					instruction->setSeg( sreg_mod01or10_rm16[rm]);
				if (ilen < remain)
				{
					// 8 sign extended to 16
					instruction->modRMForm.displ16u = (Bit8s) *iptr++;
					ilen++;
					goto modrm_done;
				}
				else
					return(0);
			}
			if (mod == 0x80)
			{ // mod == 10b
				instruction->ResolveModrm = BxResolve16Mod1or2[rm];
				if (IA32_NULL_SEG_REG(instruction->seg()))
					instruction->setSeg( sreg_mod01or10_rm16[rm]);
				if ((ilen+1) < remain)
				{
					instruction->modRMForm.displ16u = FetchWORD(iptr);
					iptr += 2;
					ilen += 2;
					goto modrm_done;
				}
				else return(0);
			}
			// mod must be 00b at this point
			instruction->ResolveModrm = BxResolve16Mod0[rm];
			if (IA32_NULL_SEG_REG(instruction->seg()))
				instruction->setSeg( sreg_mod00_rm16[rm]);
			if (rm == 0x06)
			{
				if ((ilen+1) < remain)
				{
					instruction->modRMForm.displ16u = FetchWORD(iptr);
					iptr += 2;
					ilen += 2;
					goto modrm_done;
				}
				else
					return(0);
			}
			// mod=00b rm!=6
		}

modrm_done:

		// Resolve ExecutePtr and additional opcode Attr
		ia32OpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo[b1+offset]);
		while(attr & BxGroupX)
		{
			Bit32u Group = attr & BxGroupX;
			attr &= ~BxGroupX;

			switch(Group) {
			case BxGroupN:
				OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
				break;
			case BxPrefixSSE:
				{
					/* For SSE opcodes, look into another 4 entries table
					with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
					int op = sse_prefix_index[sse_prefix];
					if (op < 0)
					{
						//BX_INFO(("fetchdecode: SSE opcode with two or more prefixes"));
						UndefinedOpcode(instruction);
					}
					OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[op]);
					break;
				}
			case BxSplitMod11b:
				/* For high frequency opcodes, two variants of the instruction are
				* implemented; one for the mod=11b case (Reg-Reg), and one for
				* the other cases (Reg-Mem).  If this is one of those cases,
				* we need to dereference to get to the execute pointer.
				*/
				OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[mod==0xc0]);
				break;
			case BxFPGroup:
				if (mod != 0xc0)  // mod != 11b
					OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
				else
				{
					int index = (b1-0xD8)*64 + (0x3f & b2);
					OpcodeInfoPtr = &(BxOpcodeInfo_FloatingPoint[index]);
				}
				break;
			default:
				break;
			}

			/* get additional attributes from group table */
			attr |= OpcodeInfoPtr->Attr;
		}

		instruction->execute = OpcodeInfoPtr->ExecutePtr;
		instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
	}
	else
	{
		instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
		instruction->IxForm.opcodeReg = b1 & 7;
	}

	if (lock)
	{
		if ((mod == 0xc0) || !(attr & Ia32_Lockable))
		{
			UndefinedOpcode(instruction);
		}
	}

	imm_mode = attr & BxImmediate;
	if (imm_mode)
	{
		switch (imm_mode)
		{
		case ia32_Immediate_Ib:
			if (ilen < remain)
			{
				instruction->modRMForm.Ib = *iptr;
				ilen++;
			}
			else
			{
				return(0);
			}
			break;
		case ia32_Immediate_Ib_SE: // Sign extend to OS size
			if (ilen < remain)
			{
				Bit8s temp8s = *iptr;
				if (instruction->os32L())
					instruction->modRMForm.Id = (Bit32s) temp8s;
				else
					instruction->modRMForm.Iw = (Bit16s) temp8s;
				ilen++;
			}
			else
			{
				return(0);
			}
			break;
		case BxImmediate_Iv: // same as BxImmediate_BrOff32
		case BxImmediate_IvIw: // CALL_Ap
			if (instruction->os32L())
			{
				if ((ilen+3) < remain)
				{
					instruction->modRMForm.Id = FetchDWORD(iptr);
					iptr += 4;
					ilen += 4;
				}
				else
					return(0);
			}
			else
			{
				if ((ilen+1) < remain)
				{
					instruction->modRMForm.Iw = FetchWORD(iptr);
					iptr += 2;
					ilen += 2;
				}
				else return(0);
			}
			if (imm_mode != BxImmediate_IvIw)
				break;
			// Get Iw for BxImmediate_IvIw
			if ((ilen+1) < remain)
			{
				instruction->IxIxForm.Iw2 = FetchWORD(iptr);
				ilen += 2;
			}
			else
			{
				return(0);
			}
			break;
		case BxImmediate_O:
			// For instructions which embed the address in the opcode.
			if (instruction->as32L())
			{
				// fetch 32bit address into Id
				if ((ilen+3) < remain)
				{
					instruction->modRMForm.Id = FetchDWORD(iptr);
					ilen += 4;
				}
				else return(0);
			}
			else
			{
				// fetch 16bit address into Id
				if ((ilen+1) < remain)
				{
					instruction->modRMForm.Id = (Bit32u) FetchWORD(iptr);
					ilen += 2;
				}
				else return(0);
			}
			if (IA32_NULL_SEG_REG(instruction->seg()))
				instruction->setSeg(IA32_SEG_REG_DS);
			break;
		case BxImmediate_Iw:
		case BxImmediate_IwIb:
			if ((ilen+1) < remain)
			{
				instruction->modRMForm.Iw = FetchWORD(iptr);
				iptr += 2;
				ilen += 2;
			}
			else
			{
				return(0);
			}
			if (imm_mode == BxImmediate_Iw) break;
			if (ilen < remain)
			{
				instruction->IxIxForm.Ib2 = *iptr;
				ilen++;
			}
			else
			{
				return(0);
			}
			break;
		case BxImmediate_BrOff8:
			if (ilen < remain)
			{
				Bit8s temp8s = *iptr;
				instruction->modRMForm.Id = temp8s;
				ilen++;
			}
			else
			{
				return(0);
			}
			break;
		case BxImmediate_BrOff16:
			if ((ilen+1) < remain)
			{
				instruction->modRMForm.Id = (Bit16s) FetchWORD(iptr);
				ilen += 2;
			}
			else
			{
				return(0);
			}
			break;
		default:
			break;
		}
	}

	instruction->setB1(b1);
	instruction->setILen(ilen);
	return(1);
}

void  IA32_CPU::BxError(Ia32_Instruction_c *i)
{
	UndefinedOpcode(i);
}

void  IA32_CPU::BxResolveError(Ia32_Instruction_c *i)
{

}
